Buffer Planning for IP Placement Using Sliced-LFF

IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7% and 37.1% in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.

EARLY BUFFER PLANNING WITH CONGESTION CONTROL USING BUFFER REQUIREMENT MAP

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a buffer planning algorithm for floor-placement design flow is presented. This algorithm creates a map of buffer requirements in various regions of the design at the floorplanning stage and then enforces the detailed placer to distribute white spaces with respect to the estimated buffer requirement map. Experimental results show that the proposed method improves the performance of attempted circuits with fewer buffers. Furthermore, results show that congestion, routability and design convergence are improved and the auxiliary loops are avoided in the proposed design flow. Our analyses and experiments show that the CPU time overhead of this algorithm is very small.