A comprehensive fault model for deep submicron digital circuits

2003 ◽  
Author(s):  
J.A. Abraham ◽  
A. Krishnamachary ◽  
R.S. Tupuri
Keyword(s):  
Digital Circuits ◽  
Fault Model ◽  
Deep Submicron

Resistive Bridge fault model evolution from conventional to ultra deep submicron

2005 ◽  
Author(s):  
I. Polian ◽  
P. Engelke ◽  
B. Becker ◽  
S. Kundu ◽  
J.-M. Galliere ◽  
...  
Keyword(s):  
Fault Model ◽  
Deep Submicron ◽  
Model Evolution

scholarly journals A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits

2008 ◽  
Vol E91-D (3) ◽  
pp. 667-674 ◽  
Author(s):  
Y. YAMATO ◽  
Y. NAKAMURA ◽  
K. MIYASE ◽  
X. WEN ◽  
S. KAJIHARA
Keyword(s):  
Fault Diagnosis ◽  
Fault Model ◽  
Deep Submicron ◽  
Diagnosis Method

POWER ESTIMATION AND POWER OPTIMAL COMMUNICATION IN DEEP SUBMICRON BUSES: ANALYTICAL MODELS AND STATISTICAL MEASURES

2002 ◽  
Vol 11 (06) ◽  
pp. 637-658 ◽  
Author(s):  
PAUL P. SOTIRIADIS ◽  
ANANTHA CHANDRAKASAN
Keyword(s):  
Analytical Model ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Power Estimation ◽  
Deep Submicron ◽  
Analytical Models ◽  
Energy Estimation ◽  
Statistical Measures ◽  
Efficiency Measures ◽  
Distribution Of Power

Reduction of power dissipation in digital circuits is a subject of research in industry and academia. A major component of power dissipation in modern microprocessors is due to their large interconnect networks which are responsible for the distribution of power and clocks as well as for the intra-chip communication. Communication is realized by data and address buses. In this paper we (i) discuss an analytical model for energy estimation in deep submicron buses, (ii) present statistical energy measures based on the analytical model, (iii) derive the energy limits of communication through buses, (iv) and introduce energy efficiency measures of communication.

Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits

2007 ◽  
Vol 54 (6) ◽  
pp. 2495-2499 ◽  
Author(s):  
Matthew J. Gadlage ◽  
Ronald D. Schrimpf ◽  
Balaji Narasimham ◽  
Bharat L. Bhuva ◽  
Paul H. Eaton ◽  
...  
Keyword(s):  
Transient Response ◽  
Digital Circuits ◽  
Deep Submicron ◽  
Single Event ◽  
Single Event Transient ◽  
Voltage Fluctuations

scholarly journals Parity Codes Used for On-Line Testing in FPGA

10.14311/788 ◽  
2005 ◽  
Vol 45 (6) ◽  
Author(s):  
P. Kubalík ◽  
H. Kubátová
Keyword(s):  
Error Detection ◽  
Digital Circuits ◽  
Fault Model ◽  
Concurrent Error Detection ◽  
Combinational Circuit ◽  
Safe Operation ◽  
On Line ◽  
Xilinx Fpga ◽  
Eda Tools

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 

Sign in / Sign up

Export Citation Format

Share Document