A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process

2015 ◽  
Author(s):  
Kelvin Yi-Tse Lai ◽  
Ming-Feng Shiu ◽  
Yi-Wen Lu ◽  
Yingchieh Ho ◽  
Yu-Chi Kao ◽  
...  
Keyword(s):  
Low Power ◽  
Sensor Fusion ◽  
Lab On A Chip ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Test Circuit ◽  
Field Programmable ◽  
Self Test ◽  
Power Sensor ◽  
Built In Self Test

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

2000 ◽  
Vol 35 (3) ◽  
pp. 337-345 ◽  
Author(s):  
A.-S. Porret ◽  
T. Melly ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Wireless Applications ◽  
High Q ◽  
Standard Cmos Process
Sign in / Sign up

Export Citation Format

Share Document