A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits

Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

A Damping-Tunable Snap System: From Dissipative Hyperchaos to Conservative Chaos

A hyperjerk system described by a single fourth-order ordinary differential equation of the form x⃜=f(x⃛,x¨,x˙,x) has been referred to as a snap system. A damping-tunable snap system, capable of an adjustable attractor dimension (DL) ranging from dissipative hyperchaos (DL<4) to conservative chaos (DL=4), is presented for the first time, in particular not only in a snap system, but also in a four-dimensional (4D) system. Such an attractor dimension is adjustable by nonlinear damping of a relatively simple quadratic function of the form Ax2, easily tunable by a single parameter A. The proposed snap system is practically implemented and verified by the reconfigurable circuits of field programmable analog arrays (FPAAs).

An Efficient and Flexible Window Function for Memristor Model and its Analog Circuit Application

The memristor is a nanostructure resistive tuning two terminal novel electronics device that has been widely explored in the area of neuromorphic computing systems, memories, digital circuits, analog circuits and many more new applications. In this article an efficient and flexible window function is presented for linear drift memristor model. Propose window function provides a unique feature (controllable window function discontinuity) to linear drift memristor model by which DPHL (Distorted Pinched Hysteresis Loop) problem is resolved and also improved the programming resistance state of the memristor. Five control parameters are introduced in the presented window function, in order to fix the pre-existing problem (like boundary effect, boundary lock and inflexibility) and make it more flexible. The programmable analog gain amplifier circuit is ultimately executed to instantiate the utilization of evolved memristor model.

FPAA-Based Realization of Filters with Fractional Laplace Operators of Different Orders

A simple and direct procedure for implementing fractional-order filters with transfer functions that contain Laplace operators of different fractional orders is presented in this work. Based on a general fractional-order transfer function that describes fractional-order low-pass, high-pass, band-pass, band-stop and all-pass filters, the introduced concept deals with the consideration of this function as a whole, with its approximation being performed using a curve-fitting-based technique. Compared to the conventional procedure, where each fractional-order Laplace operator of the transfer function is individually approximated, the main offered benefit is the significant reduction in the order of the resulting rational function. Experimental results, obtained using a field-programmable analog array device, verify the validity of this concept.

Power-Law Compensator Design for Plants with Uncertainties: Experimental Verification

A power-law compensator scheme for achieving robust frequency compensation in control systems including plants with an uncertain pole, is introduced in this work. This is achieved through an appropriate selection of the compensator parameters, which guarantee that the Nyquist diagram of the open-loop system compensator-plant crosses a fixed point independent of the plant pole variations. The implementation of the fractional-order compensator is performed through the utilization of a curve-fitting-based technique and the derived rational integer-order transfer function is realized on a Field-Programmable Analog Array device. The experimental results confirm that the the phase margin is well preserved, even for ±40% variation in the pole location of the plant.

FPAA Implementations of Fractional-Order Chaotic Systems

In this paper, fractional-order chaotic systems in an analog-based platform are realized using field programmable analog arrays (FPAA) hardware. With the help of this work, we aim to increase the complexity of chaotic systems. Approximated transfer functions in frequency domain are obtained by analyzing different values of fractional-order integrator with the Charef approximation method. In this study, fractional-order numerical calculation of Rssler and Sprott type-H chaotic systems is carried out. MATLAB Simulink model for chaotic systems that satisfy the conditions of chaos in the boundaries of fractional order value is schematically presented. Moreover, CAM designs and analysis that facilitate the realization of fractional-order transfer functions in FPAA platforms are introduced. The analog-based FPAA experimental and numerical outcomes for fractional order chaotic systems are demonstrated. The comparison of the results obtained in the numerical analysis and simulation study with the experimental results is given. This study confirms that the unpredictability of the chaos carrier signals realized by digital-based can be increased with analog-based FPAA hardware and fractional-order structures so as to provide safer transfer of information signals.

Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array.

Pragmatic Implementation of the Front-End of an N-bit/V ADC based on FPGA and FPAA

Reconfigurability has made it possible, among other benefits, to replace traditional discrete components with chips, whose internal components can be programmed in this case FPAAs (Field Programmable Analog Arrays). This paper presents a design and implementation of FPAA of the analog front end dedicated to a new ADC architecture called “N-bit/V”. After validation of the algorithm in simulation, the experimentation results show that the obtained reconfigurable circuit can replace the traditional discrete components-based circuits.