Simultaneous front and back side Cu metallization on power chips: DP: Discrete and power devices or ET/ID: Enabling technologies and innovative devices

Author(s):  
Cassandra Melvin ◽  
Bernd Roelfs
Author(s):  
Jung Kil Lee ◽  
R. Chisholm ◽  
M. van der Heijden ◽  
K. Best ◽  
P. ten Berge
Keyword(s):  

Author(s):  
Lorenzo Motta ◽  
Paolo Veneto ◽  
Mark Antolik ◽  
Donato Di Donato

Abstract Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.


2016 ◽  
Vol 5 (9) ◽  
pp. P457-P460 ◽  
Author(s):  
Milantha De Silva ◽  
Tomonori Maeda ◽  
Seiji Ishikawa ◽  
Hiroshi Sezaki ◽  
Takamichi Miyazaki ◽  
...  

Author(s):  
M. H. Rhee ◽  
W. A. Coghlan

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.


Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.


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