Application of Back-side Alignment of Thick Layers for the Manufacturing of Advanced Power Devices

2006 ◽  
Author(s):  
Jung Kil Lee ◽  
R. Chisholm ◽  
M. van der Heijden ◽  
K. Best ◽  
P. ten Berge
Keyword(s):  
Back Side ◽  
Power Devices ◽  
Thick Layers

Morphology Optimization of Very Thick 4H-SiC Epitaxial Layers

2013 ◽  
Vol 740-742 ◽  
pp. 251-254
Author(s):  
Milan Yazdanfar ◽  
Pontus Stenberg ◽  
Ian D. Booker ◽  
Ivan.G Ivanov ◽  
Henrik Pedersen ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Epitaxial Growth ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Growth Conditions ◽  
Epitaxial Layers ◽  
Power Devices ◽  
Chemical Vapor Deposition Reactor ◽  
Thick Layers

Epitaxial growth of about 200 µm thick, low doped 4H-SiC layers grown on n-type 8° off-axis Si-face substrates at growth rates around 100 µm/h has been done in order to realize thick epitaxial layers with excellent morphology suitable for high power devices. The study was done in a hot wall chemical vapor deposition reactor without rotation. The growth of such thick layers required favorable pre-growth conditions and in-situ etch. The growth of 190 µm thick, low doped epitaxial layers with excellent morphology was possible when the C/Si ratio was below 0.9. A low C/Si ratio and a favorable in-situ etch are shown to be the key parameters to achieve 190 µm thick epitaxial layers with excellent morphology.

Characterization of Grapho-Silicidation on n+4H-SiC C-Face for Back Side Ohmic Contacts of Power Devices

2016 ◽  
Vol 5 (9) ◽  
pp. P457-P460 ◽  
Author(s):  
Milantha De Silva ◽  
Tomonori Maeda ◽  
Seiji Ishikawa ◽  
Hiroshi Sezaki ◽  
Takamichi Miyazaki ◽  
...  
Keyword(s):  
Ohmic Contacts ◽  
Back Side ◽  
Power Devices

HREM observation of dislocations near room temperature fractures in silicon

1988 ◽  
Vol 46 ◽  
pp. 892-893
Author(s):  
M. H. Rhee ◽  
W. A. Coghlan
Keyword(s):  
Cross Section ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Dislocation Nucleation ◽  
Back Side ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Flat Surfaces ◽  
Induced Fractures ◽  
Vicker’S Microhardness

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.

Field Effect Modulation of Electrocatalytic Hydrogen Evolution at Back-Gated Two-Dimensional MoS2 Electrodes

2019 ◽  
Author(s):  
Yan Wang ◽  
Sagar Udyavara ◽  
Matthew Neurock ◽  
C. Daniel Frisbie
Keyword(s):  
Electric Field ◽  
Hydrogen Evolution ◽  
Active Sites ◽  
Density Functional ◽  
Electrode Materials ◽  
Density Functional Theory Calculations ◽  
Electronic Charge ◽  
Back Side ◽  
Gate Electrode ◽  
Conventional Manner

<div> <div> <div> <p> </p><div> <div> <div> <p>Electrocatalytic activity for hydrogen evolution at monolayer MoS2 electrodes can be enhanced by the application of an electric field normal to the electrode plane. The electric field is produced by a gate electrode lying underneath the MoS2 and separated from it by a dielectric. Application of a voltage to the back-side gate electrode while sweeping the MoS2 electrochemical potential in a conventional manner in 0.5 M H2SO4 results in up to a 140-mV reduction in overpotential for hydrogen evolution at current densities of 50 mA/cm2. Tafel analysis indicates that the exchange current density is correspondingly improved by a factor of 4 to 0.1 mA/cm2 as gate voltage is increased. Density functional theory calculations support a mechanism in which the higher hydrogen evolution activity is caused by gate-induced electronic charge on Mo metal centers adjacent the S vacancies (the active sites), leading to enhanced Mo-H bond strengths. Overall, our findings indicate that the back-gated working electrode architecture is a convenient and versatile platform for investigating the connection between tunable electronic charge at active sites and overpotential for electrocatalytic processes on ultrathin electrode materials.</p></div></div></div><br><p></p></div></div></div>

Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy

2006 ◽  
Author(s):  
J.S. McMurray ◽  
C.M. Molella
Keyword(s):  
The Body ◽  
Silicon On Insulator ◽  
Back Side ◽  
Cross Sectional ◽  
Plan View ◽  
Spreading Resistance ◽  
Scanning Capacitance Microscopy ◽  
Root Cause ◽  
Cross Sectional Imaging ◽  
Active Channel

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Failure Analysis of Autoclave-Stressed SRAMs with Aluminum Fuses

1999 ◽  
Author(s):  
Jamey Moss ◽  
Sam Subramanian ◽  
Vince Soorholtz ◽  
Michael Thomas ◽  
Mark Gerber ◽  
...  
Keyword(s):  
Nitric Acid ◽  
Fire Retardant ◽  
Antimony Trioxide ◽  
Back Side ◽  
New Approach ◽  
Eds Analysis ◽  
Plastic Package ◽  
Residual Aluminum ◽  
Rich Material ◽  
Static Ram

Abstract Several hundred units were subjected to autoclave stress as part of the qualification of a new fast static RAM. Many units failed after autoclave stress, and these parts recovered after conventional depotting using nitric acid and a hot plate. Based on the recovery of the units, the failures were determined to be fuse-related because the nitric acid cleared the fuse cavities during depotting. Chemical analysis after thermally extracting the die from the package revealed an antimony-rich material in failing fuse cavities. Source of the antimony was linked to antimony trioxide added to the plastic package as a fire retardant. However, it was unclear whether the antimony-rich material caused the failure or if it was an artifact of thermal depotting. A new approach that did not thermally or chemically alter the fuse cavities was employed to identify the failing fuses. This approach used a combination of back-side grinding, dimpling, and back-side microprobing. The antimony-rich material found in the fuse cavity was confirmed using SEM and TEM-based EDS analysis, and it is believed to be a major contributing factor to fuse failures. However, it is unclear whether the short was caused by the antimony-rich material or by a reaction between that material and residual aluminum (oxide) left in the fuse cavity after the laser blows.

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