Contact and non contact post-CMP cleaning of thermal oxide silicon wafers

2003 ◽  
Author(s):  
N. Moumen ◽  
M. Guarrera ◽  
C. Piboontum ◽  
A.A. Busnaina
Keyword(s):  
Silicon Wafers ◽  
Thermal Oxide

Thermal Oxide Grown on High Index Silicon Wafers

2019 ◽  
Vol 3 (33) ◽  
pp. 9-14 ◽  
Author(s):  
Ramiro Rogelio Rodríguez ◽  
Wilfrido Calleja Arriaga ◽  
Francisco Javier De la Hidalga Wade ◽  
Pedro Rosales ◽  
Alfonso Torres ◽  
...  
Keyword(s):  
Silicon Wafers ◽  
High Index ◽  
Thermal Oxide

Chemical mechanical polishing of thermal oxide films using silica particles coated with ceria

2002 ◽  
Vol 17 (10) ◽  
pp. 2744-2749 ◽  
Author(s):  
Seung-Ho Lee ◽  
Zhenyu Lu ◽  
S. V. Babu ◽  
Egon Matijević
Keyword(s):  
Chemical Mechanical Polishing ◽  
Colloidal Silica ◽  
Oxide Films ◽  
Silica Particles ◽  
Silicon Wafers ◽  
Mechanical Polishing ◽  
Thermal Oxide ◽  
Pure Ceria ◽  
Polish Rate

Thermal oxide covered silicon wafers were polished with slurries containing either nano-sized ceria (CeO2) or newly prepared uniform colloidal silica particles coated with ceria. The polish rate of the latter was significantly higher than that of pure ceria. The experiments were carried out using different concentrations of the abrasives at pH 4 and 10. Little effect on the polishing rates was noted when the conditions of the slurries were varied, which was explained by the compensation of two opposite polishing mechanisms.

The study of the thermal oxide films on silicon wafers by Fourier transform infrared attenuated total reflection spectroscopy

1990 ◽  
Vol 68 (4) ◽  
pp. 1429-1434 ◽  
Author(s):  
Yoshikatsu Nagasawa ◽  
Ichirou Yoshii ◽  
Kiyomi Naruke ◽  
Kazuhiko Yamamoto ◽  
Hideyuki Ishida ◽  
...  
Keyword(s):  
Fourier Transform ◽  
Oxide Films ◽  
Fourier Transform Infrared ◽  
Silicon Wafers ◽  
Total Reflection ◽  
Attenuated Total Reflection ◽  
Reflection Spectroscopy ◽  
Thermal Oxide

Arsenic segregation in polysilicon

1983 ◽  
Vol 41 ◽  
pp. 154-155 ◽  
Author(s):  
P.E. Batson ◽  
C.R.M. Grovenor ◽  
D.A. Smith ◽  
C. Wong
Keyword(s):  
Incident Beam ◽  
Silicon Wafers ◽  
Chemical Polishing ◽  
Bright Field Image ◽  
Beam Size ◽  
Stem Analysis ◽  
Bright Field ◽  
Twin Boundaries ◽  
X Ray ◽  
Line Scan

In this work As doped polysilicon was deposited onto (100) silicon wafers by APCVD at 660°C from a silane-arsine mixture, followed by a ten minute anneal at 1000°C, and in one case a further ten minute anneal at 700°C. Specimens for TEM and STEM analysis were prepared by chemical polishing. The microstructure, which is unchanged by the final 700°C anneal,is shown in Figure 1. It consists of numerous randomly oriented grains many of which contain twins.X-ray analysis was carried out in a VG HB5 STEM. As K α x-ray counts were collected from STEM scans across grain and twin boundaries, Figures 2-4. The incident beam size was about 1.5nm in diameter, and each of the 20 channels in the plots was sampled from a 1.6nm length of the approximately 30nm line scan across the boundary. The bright field image profile along the scanned line was monitored during the analysis to allow correlation between the image and the x-ray signal.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Sign in / Sign up

Export Citation Format

Share Document