Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs

1998 ◽  
Vol 17 (9) ◽  
pp. 803-818 ◽  
Author(s):  
N. Togawa ◽  
M. Yanagisawa ◽  
T. Ohtsuki
Keyword(s):  
Routing Algorithm ◽  
Global Routing ◽  
Technology Mapping ◽  
A Performance

A Provably Good Global Routing Algorithm in Multilayer IC and MCM Layout Designs

2009 ◽  
pp. 443-454
Author(s):  
Mohamed Saad ◽  
Tamás Terlaky ◽  
Anthony Vannelli ◽  
Hu Zhang
Keyword(s):  
Routing Algorithm ◽  
Global Routing

scholarly journals A High Performance Global Routing Algorithm on Julia Parallel Computing Platform

2021 ◽  
Vol 9 ◽  
pp. 103-108
Author(s):  
Meenakshi Agarwalla ◽  
Manash Pratim Sarma ◽  
Kandarpa Kumar Sarma
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Routing Algorithm ◽  
Global Routing ◽  
Careful Attention ◽  
Additional Advantage ◽  
C Language ◽  
Computing Platform ◽  
Sequential Processing ◽  
Design Requirements

o keep pace with the design requirements of Integrated Circuits (ICs), parallel processing is adopted. The path to be routed between two nodes may or may not be dependent on the previously routed paths. The solution requires careful attention in distributing the nets to be routed to different processors. Previous work on allocating the tasks to processors has been quite successful, reporting upto 3x improvement on 4 cores and 5x improvement on 8 core machine. The advantage of increasing the number of cores diminishes with each added processor and the challenge lies in being able to maintain the improvement per added core. The existing techniques of distributing the nets cannot provide additional advantage of using more than 8 cores. This paper improves the work on parallelizing global routing using a technique of balancing the load on the processors for better utilization of the resources. A relatively new budding platform Julia has been used which provides the ease of programming while maintaining the performance of the C language. Technique used in this paper has enabled to use 16 cores with routing solutions obtained in 0.8 minutes achieving 12.5 times speedup compared to sequential processing on a single core

Sign in / Sign up

Export Citation Format

Share Document