Advances in Wire Bonding Technology for Different Bonding Wire Material

2015 ◽  
Vol 2015 (1) ◽  
pp. 000406-000412 ◽  
Author(s):  
Ivy Qin ◽  
Aashish Shah ◽  
Hui Xu ◽  
Bob Chylak ◽  
Nelson Wong

With all the advances in 2.5D and 3D packaging, wire bonding is still the most popular interconnect technology and the workhorse of the industry. Wire bonding technology has been the lower cost solution comparing to flip chip. Wire bonding package cost is much reduced with the introduction of Copper wire bonding. Technology development and innovation in wire bonding provides new packaging solutions that improves performance and reduces cost. This paper reviews the recent innovations in ball bonding technology to provide optimized ball bonding solutions targeted for different bonding wire material. It examines the different challenges for the alternative wire types including Cu wire, Pd coated, and AuPd coated Cu wire and Ag Alloy wire. We will discuss key development in ball bonding equipment, process and material to overcome the challenges and provide robust low cost solutions. The advantages of each wire type are outlined, and guidelines to select the right bonding wire type per application requirements are provided.

2010 ◽  
Vol 2010 (1) ◽  
pp. 000462-000469
Author(s):  
Harry K. Charles

Since its very inception, the microelectronic wire bond has been the dominate form of first-level interconnection (chip to package or substrate). Wire bonds account for over 80% of first-level chip interconnections made by the microelectronic industry each year. Wire bonding is reliable, flexible, and low cost when compared to other forms of first-level interconnections. In this article a brief discussion of wire bonding is presented along with bond formation fundamentals. Aspects of wire bond reliability will be explored in conjunction with methods of wire bond testing. Particular attention is given to fine pitch bonding, bonding to stacked die, higher frequency bonding, ball bonding with copper wire, and advanced bond testing methods.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000589-000599
Author(s):  
Tu Anh Tran ◽  
Varughese Mathew ◽  
Harold Downey

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on evaluating Au and Cu wire bonding on low-K-copper wafers having two types of bonding surfaces, the conventional aluminum pad and aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold. Ni thickness ranging from 1μm to 3μm was evaluated. Defects on as-plated Ni/Pd/Au bond pads such as color difference and surface roughness were determined to be due to nodule growth and plating non-uniformity. Wire bonded strip-level thermal aging was conducted to compare the high-temperature performance of the four interconnect types. Packages underwent extensive reliability stress conditions. Cross-sectioning through the ball bonds was also conducted to examine the welding region between the ball bond and bond pad. Defects in plating and wire bonding processes causing package reliability failures were identified. Recommendations for plating and wire bonding processes were derived to ensure high quality and reliable interconnect exceeding AEC grade 0 requirements.


2014 ◽  
Vol 2014 (1) ◽  
pp. 000301-000306
Author(s):  
Hidekazu TANISAWA ◽  
Kohei HIYAMA ◽  
Takeshi ANZAI ◽  
Hiroki TAKAHASHI ◽  
Yoshinori MURAKAMI ◽  
...  

This paper reports on a flip-chip bonding technology using an aluminum bump at high temperatures, such as for SiC semiconductors. In recent years, double-sided mounting structures have been proposed for the purposes of miniaturization and low inductance. The surface mounting method requires durability to withstand high temperatures. We propose a new technique for the flip-chip bonding of an Al bump made from bonding wire. The recrystallization temperature of aluminum is under 250 °C. As a result, there is an expectation of mitigating mechanical stress between the chip and bonded substrate. A high-temperature exposure test at 250 °C for 3000 hours and a thermal-cycle test between −40 and 250 °C for 3000 cycles have been executed. Results indicate that shear strength of the Al bump meets the requirements set forth in the IEC60749-19 guideline until 2000 cycles at room temperature.


2012 ◽  
Vol 217-219 ◽  
pp. 2317-2321 ◽  
Author(s):  
Chun Yue Huang ◽  
Ying Liang ◽  
Song Wu ◽  
Tian Ming Li

The copper wire has some advantages in thermal performance, mechanical performance, and low cost, which make it can provide the lowest cost flip-chip(FC) package for low I/O density device. The 2D Cu stud bump finite element model was set up by using ANSYS/LS-DYNA with LOLID162 element to dynamic simulate the Cu stud bump bonding shaping process. The stress distribution in the Cu stud bump and the pad during the bonding process were studied, and the influence of pad thickness on the stress distribution of Si chip was also analyzed. The results shows that under the bonding process the Cu bump height is mainly influenced by the bonding pressure and the top shape of the Cu bump is influenced by ultrasonic energy, the increase of pad thickness results in reducing stress concentration inside the Si chip.


2015 ◽  
Vol 667 ◽  
pp. 250-258 ◽  
Author(s):  
Da Xu Zhao ◽  
Xian Cai ◽  
Guo Zhong Shou ◽  
Yu Qi Gu ◽  
Pei Xin Wang

As a new kind of manufacturing technology developing rapidly, Material Increasing Manufacturing, scilicet 3D printing technology is that the popularity of various fields. In this paper, under the background of the desktop 3D printing gradually enter the family. To solve the printing material problem scilicet 3D printing technology development bottleneck, come up with a bamboo-plastic composite made of Bamboo powder and poly lactic acid (PLA), can be used on desktop 3D printing. Due to bamboo resources is abundant, low cost, and also have the advantages of friendly of environment, have a good potential for development. In this paper, the right formula is used in the study on preparation of materials, through the material blending; extrusion process to produce the 3D printing wire can meet the requirements. Through further studies on the ratio of bamboo and plastic, the amount of additives added, extrusion processing temperature and material situation, optimizing the ratio of bamboo and plastic, the amount of Additives, adjust the extrusion temperature in the formulation. Tests showed that through the improved technology, wires have further enhanced performance, continuous printing more than 300 meters, the printing effect is smooth, jam does not appear, and the molded parts have good quality.


2015 ◽  
Vol 12 (2) ◽  
pp. 92-97 ◽  
Author(s):  
Hidekazu Tanisawa ◽  
Kohei Hiyama ◽  
Takeshi Anzai ◽  
Hiroki Takahashi ◽  
Yoshinori Murakami ◽  
...  

This article reports on a flip-chip bonding technology using an Al bump at high temperatures, such as for SiC semiconductors. In recent years, double-sided mounting structures have been proposed for purposes of miniaturization and low inductance. The surface-mounting method requires durability against high temperatures. We propose a new technique for the flip-chip bonding of an Al bump made from bonding wire. The recrystallization temperature of Al is under 250°C. As a result, there is an expectation of mitigating mechanical stress between the chip and the bonded substrate. We conducted a high-temperature aging test at 250°C for 3,000 h and a thermal shock test between −40°C and 250°C for 3,000 cycles. Results indicate that the shear strength of the Al bump meets the requirements specified in the IEC60749-19 guideline up to 2,000 cycles at room temperature.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001797-001828 ◽  
Author(s):  
Christophe Zinck ◽  
Jean-Marc Yannou ◽  
Jérôme Baron ◽  
Phil Garou

Renewed interest in flip-chip technologies in concurrently motivated in many application areas by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages. Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are more and more requiring footprint and weight reduction coupled with higher electrical performances (signal propagation and power distribution). The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding for good. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies. It is not any longer only about higher performance and lower cost reliable interconnect, assembly and packaging technologies: if remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore's law. In this presentation, we will first focus on Flip-Chip technologies and their evolution. We will present the main players, their facilities and technologies. We will sketch a worldwide roadmap of flip-chip featuring such varied applications as wireless digital, PC processors, RF and power devices. We will then present our market forecasts and explain how we see these innovations will modify the market of packaging interconnections and assembly in the years to come.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000667-000674 ◽  
Author(s):  
Chunyan Nan ◽  
Michael Mayer ◽  
Y. Norman Zhou ◽  
Jairus L. Pisigan ◽  
John Persic ◽  
...  

In this study, security bumps are used for strengthening the stitch bonds of two 20 micron diameter insulated Au wire bonding example processes. Bump bonding as a variant of the ball bonding process has been commonly used in the microelectronic industry to make bumps on dies that will later be flip-chip bonded. The optimized stitch bond parameters combined with the security bumps placed upon the stitch bonds substantially improve the second bond strength demonstrated on the two example processes on two different types of wire bonding equipment. A comparison of pull test results shows that security bumps increase stitch pull force up to 100%. The effect of varying the relative position (shift) of the security bump relative to the stitch bond location is investigated for one process. The window with the highest pull force improvement is ranging from 16 to 31 micron shift towards the ball bond. Looping with insulated wire is faster than with bare wire because of less effort to mitigate the risks of wires touching each other and producing a short. If two wire loops touch each other e.g. after molding, the wire insulation prevents shorts. Therefore, the looping requirements of the example processes with security bumps can be relaxed by reducing the number of kinks (reverses) from four to two. Due to the reduced looping complexity, the overall UPH increased with insulated wire by about 3.0 % and 4.9 % for the two processes, respectively. This increase is in spite of the time required for the additional security bumps, and compared to bare wire processes without security bumps but with more complex looping.


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