Mechanism and Model of Bond Formation in Ultrasonic Wire Bonding

Author(s):  
T. Calvin Tszeng

Despite being a critical phenomenon of tremendous technological significance in ultrasonic flip-chip and wire bonding processes of today’s microelectronic devices, interfacial bond formation still calls for better understanding at a fundamental level. The goal of the research is to improve these processes through better understanding and modeling of bond formation. This paper presents a micromechanics model that addresses increasing contact area during ultrasonic cyclic loading cycle. The micromechanics model provides interfacial shear stress as boundary condition to FEM simulations of ultrasonic bonding processes. Comparison between preliminary results and experimental data is conducted.

Aerospace ◽  
2005 ◽  
Author(s):  
Michael Bro¨kelmann ◽  
Jo¨rg Wallaschek ◽  
Hans J. Hesse

Quality monitoring in microelectronics becomes more and more important because of the constantly rising complexity and miniaturization of modern microelectronic devices. This paper describes a model based method for online quality monitoring in ultrasonic wire bonding. This new approach aims to reconstruct the metallophysical processes within the bonding zone by the aid of a validated analytical model of the bonding system. The model comprises a 2-DOF electromechanical analogous circuit representing the ultrasonic transducer, a phase-locked-loop controller for frequency control and time varying spring-damper elements representing the bond process. It will be shown how faulty bonds can clearly be identified by this method.


2016 ◽  
Vol 2016 (1) ◽  
pp. 000398-000401
Author(s):  
Henri Seppänen

Abstract In power electronics modules, ultrasonic wire bonding is a common method to make electronic connections between the connector pins and the IGBTs. In these modules the connector pins are often residing on top of the plastic frame. Due to the pins being in positions which are hard to reach, clamping of these pins is either suboptimal or not used. This poor or absent clamping combined with the plastic frame's elasticity (softness) means that the pin has more freedom to move compared to the bonding on a metal substrate or IC. In our experiments we measured the pin and the plastic frame displacement with a laser Doppler vibrometer during the ultrasonic heavy wire (400 um in diameter Al wire) bonding process. We measured that the press fitted pin can move laterally along the ultrasonic excitation axis (2.0 ± 0.2) um whereas the frame under the pin moved (0.3 ± 0.1) um. This indicates that the pin slips over the frame while bonding. The slipping of the pin is also visible on the ultrasonic frequency waveforms of the transducer. While molded pins in general are thought to be more stable compared to the press fitted pins, similar behavior is seen in heavy wire bonding where high ultrasonic power is needed. We measured molded frame displacement (0.6 ± 0.2) um while bonding on the pin. In this paper we show how to use process traces and visual inspection to detect unstable pins and how to improve bondability on unstable pins by selecting process parameters that are optimized for the unstable pins rather than stable surfaces.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


Author(s):  
Jiromaru TSUJINO ◽  
Masataka KURODA ◽  
Mitsuo HORIKOSHI ◽  
Hidetoshi SUGIMOTO

Author(s):  
Yangyang Long ◽  
Folke Dencker ◽  
Andreas Isaak ◽  
Friedrich Schneider ◽  
Jorg Hermsdorf ◽  
...  

Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.


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