Parameter extraction and electrical characterization of high density connector using time domain measurements

1999 ◽  
Vol 22 (1) ◽  
pp. 32-39 ◽  
Author(s):  
S. Pannala ◽  
A. Haridass ◽  
M. Swaminathan
Keyword(s):  
Time Domain ◽  
Electrical Characterization ◽  
Parameter Extraction ◽  
High Density

Challenges in Interface Trap Characterization of Deep Sub-Micron MOS Devices Using Charge Pumping Techniques

1999 ◽  
Vol 592 ◽  
Author(s):  
J.L. Autran ◽  
P. Masson ◽  
G. Ghibaudo
Keyword(s):  
Time Domain ◽  
Electrical Characterization ◽  
Time Domain Analysis ◽  
Interface Trap ◽  
Interface Traps ◽  
Electrical Behavior ◽  
Charge Pumping ◽  
Mos Devices ◽  
Technological Treatments

ABSTRACTThis work surveys some of our recent experimental and theoretical advances in charge pumping for the electrical characterization of interface traps present in MOSFET architectures. The first part of this paper is devoted to an improved time-domain analysis of the charge pumping phenomenon. This approach presents the main advantage to use the same formalism to describe the charge pumping contribution of a single trap or a continuum of traps at the Si-SiO2 interface. The implications for deepsubmicron MOSFET characterization are illustrated. Some experimental aspects are then presented, including the adaptation of the technique to ultra-thin oxides, non-planar oxides and DRAM memory cells. Finally, recent charge pumping characterization results are reported concerning the electrical behavior of the Si-SiO2 interface submitted to particular technological treatments, electrical and radiation stresses, or post-degradation anneals.

Electrical Characterization of 3C-SiC Lateral MOSFETs Fabricated on Heteroepitaxial Films Including High Density of Defects

2015 ◽  
Vol 821-823 ◽  
pp. 733-736 ◽  
Author(s):  
Yukimune Watanabe ◽  
Noriyasu Kawana ◽  
Tsuyoshi Horikawa ◽  
Kiichi Kamimura
Keyword(s):  
Gate Voltage ◽  
Light Emission ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Drain Current ◽  
High Density ◽  
Electrical Characteristics ◽  
Voltage Curve ◽  
Emission Light

We have fabricated lateral MOSFETs on heteroepitaxial 3C-SiC films included high density of defects. Electrical characteristics of 3C-SiC MOSFETs and their temperature dependence were measured to discuss effects of defects on the electrical characteristics. A field effect mobility of 156 cm2/Vs was obtained at room temperature. After applying a drain voltage of 10 V or higher, the drain current - gate voltage curve shifted toward the positive gate voltage. This shift was caused mainly by the charge trapping in the gate oxide. The light emission was observed on the surface of the active MOSFET. The spatial distribution of the emission light from MOSFETs indicated that the charge was generated at the source edge of the gate channel.

Electrical characterization of TSVs with varying process knobs and temporary bond/adhesive system robustness studies for 2.5D/3D manufacturing

2013 ◽  
Vol 2013 (1) ◽  
pp. 000233-000233
Author(s):  
Niranjan Kumar
Keyword(s):  
Electrical Parameter ◽  
Electrical Characterization ◽  
Adhesive System ◽  
Parameter Extraction ◽  
Electrical Performance ◽  
Process Window ◽  
Film Properties ◽  
Wafer Processing ◽  
The Impact

TSVs are used to carry power/ground and signals straight to the heart of the logic/memory devices where all the intricate and busy architectures lie. I consider it like the downtown area inside a city where the real estate is more expensive and requires intricate design and execution. As a result in case of the TSVs, there is no room for electrical degradation and stress interaction with transistor devices (keep out zone). The Cu protrusion, it's interaction with the intricate local interconnects (M1 and below structures), the current leakage, capacitance, reliability, become highly critical to fully achieve the power per watt advantage of the TSVs. As a result, a thorough electrical characterization of TSVs with varying film properties and the process window becomes very critical for integration with the 20nm node (and below) devices. In this paper we will discuss implementation of modified oxide liner, barrier/seed, ECD fill and CMP of films to achieve robust TSVs for electrical parameter extraction. We will closely examine the impact of these film properties on the electrical performance and its repeatability to achieve wide process windows. Such studies are expected to improve manufacturing yields of TSV product wafers at fabs/foundries. Alternately, we will present detailed metrology studies of two temporary bond method/adhesive systems as it progresses through the thin wafer downstream processes (via-reveal processes). This exercise is targeted to address productivity and yield challenges with thin wafer processing (backside via-reveal process). We will attempt to demonstrate a robust temporary bond/adhesive system that exhibits no thin wafer damage/wrinkling and no edge profile degradation issues over repeated runs (production like). This study will help to characterize the adhesive and low temperature passivation film interfaces in details to support the thin wafer processing robustness for TSV manufacturing.

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

2013 ◽  
Vol 90 ◽  
pp. 86-93 ◽  
Author(s):  
D.-Y. Jeon ◽  
S.J. Park ◽  
M. Mouis ◽  
M. Berthomé ◽  
S. Barraud ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Parameter Extraction ◽  
Junctionless Transistors
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