High performance 0.35 /spl mu/m gate-length monolithic enhancement/depletion-mode metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As HEMTs on GaAs substrates

2001 ◽  
Vol 22 (8) ◽  
pp. 364-366 ◽  
Author(s):  
D.C. Dumka ◽  
W.E. Hoke ◽  
P.J. Lemonias ◽  
G. Cueva ◽  
I. Adesida
Keyword(s):  
High Performance ◽  
Gate Length ◽  
Gaas Substrates

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

Sub-5 nm monolayer germanium selenide (GeSe) MOSFETs: towards a high performance and stable device

Nanoscale ◽  
2020 ◽  
Vol 12 (28) ◽  
pp. 15443-15452
Author(s):  
Ying Guo ◽  
Feng Pan ◽  
Gaoyang Zhao ◽  
Yajie Ren ◽  
Binbin Yao ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Device Performance ◽  
Gate Length ◽  
Germanium Selenide ◽  
Technology Roadmap

ML GeSe field-effect transistors have an excellent device performance, even at the 1 nm gate-length. The on-state current of the devices can fulfill the requirements of the International Technology Roadmap for Semiconductors (2013 version).

High-performance InP/In/sub 0.53/Ga/sub 0.47/As/InP double HBTs on GaAs substrates

2002 ◽  
Vol 23 (6) ◽  
pp. 297-299 ◽  
Author(s):  
Y.M. Kim ◽  
M. Dahlstrom ◽  
S. Lee ◽  
A.J.W. Rodwell ◽  
A.C. Gossard
Keyword(s):  
High Performance ◽  
Gaas Substrates

High performance resonant tunnelling structures on GaAs substrates

1990 ◽  
Vol 26 (5) ◽  
pp. 340 ◽  
Author(s):  
H. Riechert ◽  
D. Bernklau ◽  
J.-P. Reithmaier ◽  
R.D. Schnell
Keyword(s):  
High Performance ◽  
Resonant Tunnelling ◽  
Gaas Substrates

High Performance HFET Devices on Sapphire and SiC: Passivation with AlN

2002 ◽  
Vol 743 ◽  
Author(s):  
Jennifer A. Bardwell ◽  
Ying Liu ◽  
James B. Webb ◽  
Haipeng Tang ◽  
Stephen J. Rolfe ◽  
...  
Keyword(s):  
High Performance ◽  
Electron Gas ◽  
Drain Current ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Dimensional Electron ◽  
Frequency Responses ◽  
Current Collapse ◽  
Dimensional Electron Gas ◽  
Load Pull

ABSTRACTAlGaN/GaN two dimensional electron gas (2DEG) heterostructures were grown by ammonia-MBE on sapphire and SiC substrates. Devices fabricated from these optimized HFET layers, with optically defined gates showed excellent characteristics, e.g. a maximum drain current density of 1.3 A/mm, maximum transconductance of 220 mS/mm, fT of 15.6 GHz and fMAX of 58.1 GHz was measured for devices with 0.9 μm gate length and 40 μm gate width. Shorter gate length devices exhibited higher frequency responses: fT of 68 GHz and fMAX of 125 GHz for 0.25 μm gate length and fT of 103 GHz and fMAX of 170 GHz for 0.15 μm gate length. However, these devices showed “current collapse” when subjected to load pull measurements. Current collapse was also observed in sequentially repeated DC measurements in the dark, both on sapphire and SiC substrates, although the degree of collapse varied greatly from one wafer to another. One method of reducing the current collapse was to apply a thin (100 - 6000 Å) magnetron sputtered AlN passivation layer (over the gates) or a 500 Å layer under the gates so that MISFET devices were obtained. The electrical characteristics of the passivated and unpassivated devices are discussed.

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

2005 ◽  
Vol 26 (11) ◽  
pp. 823-825 ◽  
Author(s):  
Yu-Ming Lin ◽  
J. Appenzeller ◽  
Zhihong Chen ◽  
Zhi-Gang Chen ◽  
Hui-Ming Cheng ◽  
...  
Keyword(s):  
Carbon Nanotube ◽  
High Performance ◽  
Gate Length ◽  
Dual Gate ◽  
Carbon Nanotube Fets
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