1995 Symposium on VLSI Technology. Digest of Technical Papers
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Published By Japan Soc. Appl. Phys

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Characteristics of CMOSFETs with sputter-deposited W/TiN stack gate

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520886 ◽

2002 ◽

Cited By ~ 4

Author(s):

D.H. Lee ◽

S.H. Joo ◽

G.H. Lee ◽

J. Moon ◽

T.E. Shim ◽

...

Keyword(s):

Sputter Deposited

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Highly porous interlayer dielectric for interconnect capacitance reduction

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520858 ◽

2002 ◽

Cited By ~ 9

Author(s):

S.-P. Jeng ◽

K. Taylor ◽

T. Seha ◽

M.-C. Chang ◽

J. Fattaruso ◽

...

Keyword(s):

Interlayer Dielectric ◽

Porous Interlayer ◽

Highly Porous

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A new method to monitor gate-oxide reliability degradation

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520869 ◽

2002 ◽

Cited By ~ 4

Author(s):

K.P. Cheung

Keyword(s):

Gate Oxide ◽

New Method ◽

Oxide Reliability

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Reoxidized nitric oxide (ReoxNO) process and its effect on the dielectric reliability of the LOCOS edge

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520859 ◽

2002 ◽

Author(s):

B. Maiti ◽

P.J. Tobin ◽

Y. Okada ◽

S. Ajuria ◽

K.G. Reid ◽

...

Keyword(s):

Nitric Oxide

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High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxide

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520882 ◽

2002 ◽

Author(s):

S. Ohkubo ◽

Y. Tamura ◽

R. Sugino ◽

T. Nakanishi ◽

Y. Sugita ◽

...

Keyword(s):

Gate Oxide ◽

Native Oxide ◽

High Quality ◽

Pre Treatment

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Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520876 ◽

2002 ◽

Cited By ~ 9

Author(s):

A. Mujtaba ◽

S.-I. Takagi ◽

R. Dutton

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A symmetric 0.25 μm CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520860 ◽

2002 ◽

Cited By ~ 1

Author(s):

D.M. Boulin ◽

W.M. Mansfield ◽

K.J. O'Connor ◽

J. Bevk ◽

D. Brasen ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Cmos Technology

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A high performance 16M DRAM on a thin film SOI

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520898 ◽

2002 ◽

Author(s):

Hyoung-Sub Kim ◽

Sang-Bo Lee ◽

Dong-Uk Choi ◽

Jae-Hoon Shim ◽

Kyu-Han Lee ◽

...

Keyword(s):

Thin Film ◽

High Performance

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Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520835 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Yoshitomi ◽

M. Saito ◽

T. Ohguro ◽

M. Ono ◽

H.S. Momose ◽

...

Keyword(s):

High Performance ◽

Gate Length

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Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

1995 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1995.520862 ◽

2002 ◽

Author(s):

K. Yamashita ◽

H. Nakaoka ◽

K. Kurimoto ◽

H. Umimoto ◽

S. Odanaka

Keyword(s):

Low Voltage

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1995 Symposium on VLSI Technology. Digest of Technical PapersLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Japan Soc. Appl. Phys

Characteristics of CMOSFETs with sputter-deposited W/TiN stack gate

Highly porous interlayer dielectric for interconnect capacitance reduction

A new method to monitor gate-oxide reliability degradation

Reoxidized nitric oxide (ReoxNO) process and its effect on the dielectric reliability of the LOCOS edge

High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxide

Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs

A symmetric 0.25 μm CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography

A high performance 16M DRAM on a thin film SOI

Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs

Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

1995 Symposium on VLSI Technology. Digest of Technical Papers
Latest Publications