1800 V NPN bipolar junction transistors in 4H-SiC

2001 ◽  
Vol 22 (3) ◽  
pp. 124-126 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
A.K. Agarwal ◽  
R. Singh ◽  
J.W. Palmour
2017 ◽  
Vol 897 ◽  
pp. 579-582
Author(s):  
Sethu Saveda Suvanam ◽  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Carl Mikael Zetterling ◽  
Anders Hallén

In this work, total dose effects on 4H-SiC bipolar junction transistors (BJT) are investigated. Three 4H-SiC NPN BJT chips are irradiated with 3MeV protons with a dose of 1×1011, 1×1012 and 1×1013 cm-2, respectively. From the measured reciprocal current gain it is observed that 4H-SiC NPN BJT exposed to protons suffer both displacement damage and ionization, whereas, a traditional Si BJT suffers mainly from displacement damage. Furthermore, bulk damage introduction rates for SiC BJT were extracted to be 3.3×10-15 cm2, which is an order of magnitude lower compared to reported Si values. Finally, from detailed analysis of the base current at low injection levels, it is possible to distinguish when surface recombination leakage is dominant over bulk recombination.


2010 ◽  
Vol 645-648 ◽  
pp. 1025-1028 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Robert Callanan ◽  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
...  

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.


2008 ◽  
Vol 55 (6) ◽  
pp. 3055-3059 ◽  
Author(s):  
E. Bielejec ◽  
G. Vizkelethy ◽  
R. M. Fleming ◽  
W. R. Wampler ◽  
S. M. Myers ◽  
...  

1970 ◽  
Vol 108 (2) ◽  
pp. 51-54 ◽  
Author(s):  
A. Baskys ◽  
L. Nickelson ◽  
R. Navickas

The analytical method for differential amplifier offset voltage analysis is presented in the work. The method is developed for the amplifier based on the bipolar junction transistors that operate at high-current density. The transistor model based on the equation of the junction, which takes into account the dependence of majority carrier boundary concentrations on junction voltage that should be considered at high-current density, is used as the base for derivation of input offset voltage equations. The derived equations are valid in the narrow region of current, at which the differential amplifier input offset voltage measurement is provided. The obtained equations allow us to estimate the input offset voltage reduction ways. The results gained using suggested analytical analysis method are confirmed by the numerical investigation of the differential amplifier. Ill. 3, bibl. 11 (in English; abstracts in English and Lithuanian).http://dx.doi.org/10.5755/j01.eee.108.2.144


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