Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

1998 ◽  
Vol 19 (9) ◽  
pp. 348-350 ◽  
Author(s):  
Jiunn-Yann Tsai ◽  
Ying Shi ◽  
S. Prasad ◽  
S.W.-C. Yeh ◽  
R. Rakkhit
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Thickness Increase ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness

Direct evidence of gate oxide thickness increase in tungsten polycide processes

1991 ◽  
Vol 12 (11) ◽  
pp. 623-625 ◽  
Author(s):  
S.L. Hsu ◽  
L.M. Liu ◽  
M.S. Lin ◽  
C.Y. Chang
Keyword(s):  
Direct Evidence ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Thickness Increase ◽  
Gate Oxide Thickness

A Model of Threshold Voltage in FinFET

2011 ◽  
Vol 216 ◽  
pp. 167-170
Author(s):  
Jian Liu ◽  
Li Li ◽  
X.H. Zhang
Keyword(s):  
Numerical Simulation ◽  
Threshold Voltage ◽  
Doping Concentration ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Threshold Voltage Model

A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Enhancement ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Interface Traps ◽  
Low Field ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Thin Gate Oxide

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

2007 ◽  
Vol 28 (3) ◽  
pp. 217-219 ◽  
Author(s):  
Meishoku Masahara ◽  
Radu Surdeanu ◽  
Liesbeth Witters ◽  
Gerben Doornbos ◽  
Viet H. Nguyen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Slope ◽  
Gate Oxide Thickness

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

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