An analytical CMOS inverter delay model including channel-length modulations

1992 ◽  
Vol 27 (9) ◽  
pp. 1303-1306 ◽  
Author(s):  
Hwang-Cherng Chow ◽  
Wu-Shiung Feng
Keyword(s):  
Channel Length ◽  
Delay Model ◽  
Cmos Inverter

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

CMOS Inverter Degradation Delay Model

2005 ◽  
pp. 75-126
Author(s):  
Jorge Juan Chico ◽  
Alejandro Millán Calderón
Keyword(s):  
Delay Model ◽  
Cmos Inverter

scholarly journals Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

2007 ◽  
Vol 8 (1) ◽  
pp. 21-25 ◽  
Author(s):  
Zhi-Yuan Cui ◽  
Nam-Soo Kim ◽  
Hyung-Gyoo Lee ◽  
Kyoung-Won Kim
Keyword(s):  
Channel Length ◽  
Cmos Inverter ◽  
Switching Characteristic
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