scholarly journals Analytical transient response and propagation delay model for nanoscale CMOS inverter

2009 ◽  
Author(s):  
Yangang Wang ◽  
Mark Zwolinski
Keyword(s):  
Transient Response ◽  
Propagation Delay ◽  
Delay Model ◽  
Cmos Inverter ◽  
Nanoscale Cmos

CMOS Inverter Degradation Delay Model

2005 ◽  
pp. 75-126
Author(s):  
Jorge Juan Chico ◽  
Alejandro Millán Calderón
Keyword(s):  
Delay Model ◽  
Cmos Inverter

scholarly journals Revision of the Atmospheric Modeling for SNR Observations in Ground-Based GNSS Reflectometry

2020 ◽  
Author(s):  
Jörg Reinking
Keyword(s):  
Numerical Experiments ◽  
Propagation Delay ◽  
Atmospheric Modeling ◽  
Delay Model ◽  
Atmospheric Refraction ◽  
Data Analyses ◽  
Coastal Sea ◽  
Gnss Reflectometry ◽  
Ray Bending ◽  
Operational Tool

The application of signal-to-noise (SNR) observations from ground-based GNSS Reflectometry is becoming an operational tool for coastal sea-level altimetry. As in all data analyses, systematic influences must be reduced here too, to achieve reliable results. A prominent influence results from atmospheric refraction. Different approaches exist to describe or to correct for this influence. In our contribution we will revise the latest developments and suggest a simple atmospheric interferometric delay model that takes into account ray bending as well as along-path propagation delay. The findings are double-checked by numerical experiments based on a step-by-step raytracing procedure.

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

Sign in / Sign up

Export Citation Format

Share Document