Design-oriented delay model for CMOS inverter

2012 ◽  
Author(s):  
Felipe S. Marranghello ◽  
Andre I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Delay Model ◽  
Cmos Inverter

CMOS Inverter Degradation Delay Model

2005 ◽  
pp. 75-126
Author(s):  
Jorge Juan Chico ◽  
Alejandro Millán Calderón
Keyword(s):  
Delay Model ◽  
Cmos Inverter

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

An analytical CMOS inverter delay model including channel-length modulations

1992 ◽  
Vol 27 (9) ◽  
pp. 1303-1306 ◽  
Author(s):  
Hwang-Cherng Chow ◽  
Wu-Shiung Feng
Keyword(s):  
Channel Length ◽  
Delay Model ◽  
Cmos Inverter

scholarly journals Delay Time Estimation Model for Large Digital CMOS Circuits

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 161-173 ◽  
Author(s):  
Dong-Wook Kim ◽  
Tae-Yong Choi
Keyword(s):  
Delay Time ◽  
Time Estimation ◽  
Cmos Circuits ◽  
Delay Model ◽  
Estimation Model ◽  
Cmos Inverter ◽  
Digital Cmos ◽  
Modeling Process ◽  
Proposed Model ◽  
Design Cycle

Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.

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