Logic-Timing Simulation and the Degradation Delay Model
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Published By PUBLISHED BY IMPERIAL COLLEGE PRESS AND DISTRIBUTED BY WORLD SCIENTIFIC PUBLISHING CO.

9781860945892, 9781860947360

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Gate-Level DDM

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0005 ◽

2005 ◽

pp. 127-179

Author(s):

Jorge Juan Chico ◽

Alejandro Millán Calderón

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CMOS Inverter Degradation Delay Model

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0004 ◽

2005 ◽

pp. 75-126

Author(s):

Jorge Juan Chico ◽

Alejandro Millán Calderón

Keyword(s):

Delay Model ◽

Cmos Inverter

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Degradation and Inertial Effects

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0003 ◽

2005 ◽

pp. 47-74

Author(s):

Manuel Jesús Bellido Díaz ◽

David Guerrero Martos

Keyword(s):

Inertial Effects

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Delay Models: Evolution and Trends

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0002 ◽

2005 ◽

pp. 23-45

Author(s):

Manuel Jesús Bellido Díaz ◽

David Guerrero Martos

Keyword(s):

Delay Models

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Accurate Measurement of the Switching Activity

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0008 ◽

2005 ◽

pp. 227-250

Author(s):

Carmen Baena Oliva ◽

Manuel Valencia Barrero

Keyword(s):

Switching Activity

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DDM Simulation Results

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0007 ◽

2005 ◽

pp. 203-226

Author(s):

Manuel Jesús Bellido Díaz ◽

Paulino Ruiz de Clavijo Vázquez

Keyword(s):

Simulation Results

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Fundamentals of Timing Simulation

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0001 ◽

2005 ◽

pp. 1-21

Author(s):

Carlos Jesús Jiménez Fernández ◽

Manuel Valencia Barrero

Keyword(s):

Timing Simulation

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FRONT MATTER

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_fmatter ◽

2005 ◽

pp. i-xvii

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BACK MATTER

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_bmatter ◽

2005 ◽

pp. 251-267

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Logic Level Simulator Design and Implementation

Logic-Timing Simulation and the Degradation Delay Model ◽

10.1142/9781860947360_0006 ◽

2005 ◽

pp. 181-201

Author(s):

Jorge Juan Chico ◽

Paulino Ruiz de Clavijo Vázquez

Keyword(s):

Design And Implementation ◽

Simulator Design ◽

Logic Level

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Logic-Timing Simulation and the Degradation Delay ModelLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By PUBLISHED BY IMPERIAL COLLEGE PRESS AND DISTRIBUTED BY WORLD SCIENTIFIC PUBLISHING CO.

Gate-Level DDM

CMOS Inverter Degradation Delay Model

Degradation and Inertial Effects

Delay Models: Evolution and Trends

Accurate Measurement of the Switching Activity

DDM Simulation Results

Fundamentals of Timing Simulation

FRONT MATTER

BACK MATTER

Logic Level Simulator Design and Implementation

Logic-Timing Simulation and the Degradation Delay Model
Latest Publications