Materials to integrate the solder reflow and underfill encapsulation processes for flip chip on board assembly

1998 ◽  
Vol 21 (1) ◽  
pp. 57-65 ◽  
Author(s):  
D. Gamota ◽  
C. Melton
Keyword(s):  
Flip Chip ◽  
Solder Reflow

A review on solder reflow and flux application for flip chip

2017 ◽  
Author(s):  
Sarveshvaran Suppiah ◽  
Nestor Rubio Ong ◽  
Zaliman Sauli ◽  
Karunavani Sarukunaselan ◽  
Jesselyn Barro Alcain ◽  
...  
Keyword(s):  
Flip Chip ◽  
Solder Reflow

The Study on The Under Bump Metallurgy (Ubm) and 63SN-37PB Solder Bumps Interface for Flip Chip Interconnection

1998 ◽  
Vol 515 ◽  
Author(s):  
Se-Young Jang ◽  
Kyung-Wook Paik
Keyword(s):  
Shear Strength ◽  
Direct Contact ◽  
Flip Chip ◽  
Organic Substrates ◽  
Adhesion Properties ◽  
Ball Shear ◽  
Solder Bumps ◽  
Diffusion Barrier Layer ◽  
Solder Reflow ◽  
Ball Shear Strength

ABSTRACTIn the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

The effect of underfill on thermal stresses on logic ASIC and its electrical performance

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Babak Talebanpour ◽  
Doug Link
Keyword(s):  
Frequency Shift ◽  
Flip Chip ◽  
Thermal Stresses ◽  
Electrical Performance ◽  
Shear Stresses ◽  
Normal Stresses ◽  
Clock Frequency ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Reflow

Flip chip technology is widely used today to support the demand for high interconnect density of modern microelectronic circuits. Conventionally, solder bumps have provided the electrical and mechanical connection between the chip and the substrate. The solder bumps are prone to fatigue and failure especially in large chips and/or mobile devices. Conventional underfilling process which consists of flowing an epoxy under the chip and curing it after the flip chip connections are made mechanically supports the assembly, significantly reducing the shear stresses on the bumps and minimizing the chip warpage due to thermal stresses. However, underfill also has side effects. The flow of underfill depends on a lot of parameters usually can be incomplete or containing a lot of voids, inconsistent underfill results in unpredictable overall durability or manufacturing survivability. Furthermore, underfilling introduces certain components of stress, this form of stress can have adverse effect on the electrical performance of the die if it occurs close to stress sensitive parts. In this study, the effect of underfilling and its quality on the clock frequency shift of a DSP (Digital Signal Processor) chip used by Starkey Hearing Technologies is investigated. Clock frequency measurements after a solder reflow process has been compared for different underfill materials, and underfill quality. Finite element analysis was implemented to assess the stress transferred to the clock circuit on the die and examine how existence of underfill, bump height, location of bumps, and underfill voids affect the stress. The following results have been concluded based on the work presented in this paper:The conventional underfilling process for dies with very small standoff heights can be very in consistent, strongly depending on the gap uniformity, flex traces, cleanliness of the package after solder reflow, etc. large percentage of delamination and voids can occur. The voids and delamination can cause solder extrusion as well as inconsistent stress distribution on the die.Although underfilling causes large normal stresses on the die, it reduces the effective stress on the die which can translate to less warpage and the problems associated with it.The height of the bumps does not strongly affect the amount of stress build up on the die if it does not compromise a uniform underfill.Relocation of the bumps away from the clock circuit significantly reduces the stress on the clock, and it has been shown to minimize the clock shift in practice. A minimum amount of distance between the clock circuit and solder bumps should be considered when DSP layout are designed.If the clock circuit surface is not in contact with the underfill, normal stresses will not be transferred to the clock circuit minimizing the clock frequency shift. The best approach to implement this method is wafer-level underfill technique. The underfill will be applied at the wafer fab and precision lasers can cut the underfill laminate at desired locations. This process can guarantee support for the die by a uniform underfill, while stress sensitive parts will be protected against unwanted thermal stresses.

Development of a stress compensation layer for thin pixel modules 3D assembly

2014 ◽  
Vol 2014 (1) ◽  
pp. 000787-000793 ◽  
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.

Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

2015 ◽  
Vol 12 (1) ◽  
pp. 29-36
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.

The Mechanics and Impact of Hygroscopic Swelling of Polymeric Materials in Electronic Packaging

2002 ◽  
Vol 124 (2) ◽  
pp. 122-126 ◽  
Author(s):  
E. H. Wong ◽  
R. Rajoo ◽  
S. W. Koh ◽  
T. B. Lim
Keyword(s):  
Thermal Stress ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Polymeric Materials ◽  
Packaging Materials ◽  
Excellent Correlation ◽  
Reliable Technique ◽  
Hygroscopic Swelling ◽  
Solder Reflow ◽  
Swelling Characteristics

A reliable technique for characterizing the hygroscopic swelling of materials has been developed and used to characterize a number of packaging materials. Using these data, hygroscopic stress modeling were performed. The hygroscopic stress induced through moisture conditioning was found to be significant compared to the thermal stress during solder reflow. Hygroscopic stress in over-molded wire bond PBGA and molded Flip Chip PBGA was found to be 1.3 times to 1.5 times that of thermal stress. Hygroscopic swelling of the underfill in FCPBGA was found to be the main failure driver during autoclave test. Autoclave performance of FCPBGA package assembled with different underfills and chips were analyzed. Excellent correlation was found between autoclave performance and the hygroscopic swelling characteristics of the underfills.

scholarly journals Solder reflow process induced residual warpage measurement and its influence on reliability of flip-chip electronic packages

2006 ◽  
Vol 46 (2-4) ◽  
pp. 512-522 ◽  
Author(s):  
Se Young Yang ◽  
Young-Doo Jeon ◽  
Soon-Bok Lee ◽  
Kyung-Wook Paik
Keyword(s):  
Flip Chip ◽  
Electronic Packages ◽  
Reflow Process ◽  
Solder Reflow

Translation Solder Self-Alignment Mechanics Modeling for a Flip Chip in the Presence of a Viscous Fluid

2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Brett Fennell ◽  
Sangil Lee ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Viscous Forces ◽  
Solder Interconnects ◽  
Flip Chips ◽  
Modeling Process ◽  
Mass Damper ◽  
Solder Reflow ◽  
Underfill Flow ◽  
Parametric Studies ◽  
Time Required

Conventional flip chip on board processing involves four major steps: flux application, solder reflow, underfill flow, and underfill cure. The latter two steps are particularly time consuming. To address this issue, a new flip chip process has been developed in which underfill is dispensed prior to chip placement or directly on the wafer and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacturing. However, the presence of the underfill can affect the flip chips’ capacity for self-alignment. Self-alignment occurs in controlled collapse bonding when the solder interconnects become liquidus and, driven by surface tension, pull the chip into registration with the substrate. To study flip chip self-alignment in the presence of underfill, the viscous forces acting on the chip during realignment are modeled after Couette flow and the overall system is modeled as a spring-mass-damper. This paper details the modeling process and includes parametric studies to predict those conditions that are more conducive to alignment, as well as those which are not.

Predicting Technique of Delamination at Adhesively Bonding Joints in a Flip Chip Package During Solder Reflow Process

2005 ◽  
Author(s):  
Toru Ikeda ◽  
Won-Keun Kim ◽  
Noriyuki Miyazaki
Keyword(s):  
Stress Intensity ◽  
Vapor Pressure ◽  
Quantitative Evaluation ◽  
Flip Chip ◽  
Moisture Absorption ◽  
Solder Joints ◽  
Reflow Process ◽  
Sensitivity Tests ◽  
Solder Reflow ◽  
Chip Size

Recently, adhesively bonding techniques such as the anisotropic conductive film (ACF) or the non-conductive adhesive resin are often used for connections in the chip size packages instead of conventional solder joints due to their reasonable cost and the ease of miniaturization. Adhesively bonding techniques expected to be a key technology for the chip size packaging and the system in package. However, the level of reliability for adhesively bonding techniques is still less than that for solder joints. The quantitative evaluation techniques for the reliability of adhesively bonding techniques are desired. This paper focused on the reliability of adhesively bonding joints in a flip chip package during the solder reflow process for other solder jointed devices. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. The delamination toughnesses between components in a flip chip based on the stress intensity factors were measured by fracture tests in conjunction with the numerical analysis developed in our previous study. Moisture concentration after moisture absorption was expected by the diffusion analysis using the finite element method. Then, vapor pressure in a flip chip during the solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. The delaminations in an actual flip chip package during moisture/reflow sensitivity tests have successfully predicted by the present methodology.

Experiments on Fluid Mechanics in Flip-Chip Solder Connections

2003 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Experimental Finding ◽  
Numerical Study ◽  
Void Formation ◽  
Molten Solder ◽  
Bottom Edge ◽  
Solder Bumps ◽  
Solder Reflow ◽  
Heating Profiles ◽  
Bottom To Top

This experimental research studies the formation of void bubbles within molten solder bumps in flip-chip connections. A theory based on thermocapillary flow reveals that the direction of heating influences void formation. Twelve chip-bump substrate assemblies were investigated using different heating profiles. A database on sizes and locations of voids in solder bumps was constructed. The observation on cases with melting direction from bottom to top supports the numerical study based on thermocapillary theory. The results show that a single big void is near the bump center with a few small voids near the edge when the melting direction is from bottom to top during solder reflow. When the melting direction was reversed, many small voids appear near the bottom edge with big voids in the middle of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory. However, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

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