Device simulation of charge collection and single-event upset

1996 ◽  
Vol 43 (2) ◽  
pp. 561-575 ◽  
Author(s):  
P.E. Dodd
2008 ◽  
Vol 55 (4) ◽  
pp. 2126-2132 ◽  
Author(s):  
Simon Platt ◽  
ZoltÁn Torok ◽  
Chris D. Frost ◽  
Stuart Ansell

1994 ◽  
Vol 41 (6) ◽  
pp. 2203-2209 ◽  
Author(s):  
E. Normand ◽  
D.L. Oberg ◽  
J.L. Wert ◽  
J.D. Ness ◽  
P.P. Majewski ◽  
...  

1998 ◽  
Vol 84 (2) ◽  
pp. 690-703 ◽  
Author(s):  
Joseph S. Melinger ◽  
Dale McMorrow ◽  
A. B. Campbell ◽  
Stephen Buchner ◽  
Lan Hu Tran ◽  
...  

2021 ◽  
Author(s):  
Li Dong-Qing ◽  
Liu Tian-Qi ◽  
Zhao Pei-Xiong ◽  
Wu Zhen-Yu ◽  
Wang Tie-Shan ◽  
...  

Abstract 3D TCAD simulations demonstrated that reducing the distance between the well boundary and NMOS or PMOS can mitigate the cross section of Single Event Upset (SEU) in 14 nm CMOS bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restore currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Different from Dual-interlock cells (DICE) design, under the presence of enough taps to ensure the rapid recovery of well potential, this approach is more effective under heavy ion irradiation of higher LET. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.


2008 ◽  
Vol 55 (6) ◽  
pp. 2943-2947 ◽  
Author(s):  
J. D. Black ◽  
D. R. Ball II ◽  
W. H. Robinson ◽  
D. M. Fleetwood ◽  
R. D. Schrimpf ◽  
...  

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