1996 Symposium on VLSI Technology. Digest of Technical Papers
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Published By Widerkehr & Associates

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A manufacturable 0.30 μm gate CMOS technology for high speed microprocessors

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507857 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Appel ◽

S. Crank ◽

Y. Kim ◽

C. Scharrer ◽

D. Spratt ◽

...

Keyword(s):

High Speed ◽

Cmos Technology

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A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507843 ◽

2002 ◽

Cited By ~ 9

Author(s):

J.P. John ◽

V. Ilderem ◽

Changhae Park ◽

J. Teplik ◽

K. Klein ◽

...

Keyword(s):

Low Voltage

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Copper interconnection deposition techniques and integration

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507789 ◽

2002 ◽

Author(s):

Gang Bai ◽

Chien Chiang ◽

N. Cox ◽

Sychyi Fang ◽

D.S. Gardner ◽

...

Keyword(s):

Copper Interconnection ◽

Deposition Techniques

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An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 μm interconnects

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507803 ◽

2002 ◽

Cited By ~ 1

Author(s):

G.A. Dixit ◽

K.J. Taylor ◽

A. Singh ◽

C.K. Lee ◽

G.B. Shinn ◽

...

Keyword(s):

High Performance ◽

Low Resistance ◽

Polymer Dielectric ◽

Low K

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A 50 GHz implanted base silicon bipolar technology with 35 GHz static frequency divider

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507812 ◽

2002 ◽

Cited By ~ 12

Author(s):

J. Bok ◽

A. Felder ◽

T.F. Meister ◽

M. Franosch ◽

K. Aufinger ◽

...

Keyword(s):

Frequency Divider ◽

Bipolar Technology ◽

Silicon Bipolar Technology

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Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507818 ◽

2002 ◽

Cited By ~ 8

Author(s):

T. Kachi ◽

T. Kaga ◽

S. Wakahara ◽

D. Hisamoto

Keyword(s):

Low Power ◽

Threshold Voltage ◽

High Speed ◽

Back Gate ◽

Variable Threshold ◽

Gate Electrodes

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Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507830 ◽

2002 ◽

Cited By ~ 14

Author(s):

S.E. Thompson ◽

P.A. Packan ◽

M.T. Bohr

Keyword(s):

Drive Current

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NURA: a feasible, gas-dielectric interconnect process

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507801 ◽

2002 ◽

Cited By ~ 7

Author(s):

M.B. Anand ◽

M. Yamada ◽

H. Shibata

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Fully self-aligned 6F/sup 2/ cell technology for low cost 1Gb DRAM

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507778 ◽

2002 ◽

Author(s):

M. Aoki ◽

T. Ozaki ◽

T. Yamada ◽

H. Kawaguchiya ◽

Y. Ishibashi ◽

...

Keyword(s):

Low Cost ◽

Cell Technology

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Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

1996 Symposium on VLSI Technology. Digest of Technical Papers ◽

10.1109/vlsit.1996.507808 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Aton ◽

J. Seitchik ◽

K. Joyner ◽

T. Houston ◽

H. Shichijo

Keyword(s):

Direct Measurement ◽

Alpha Particles ◽

Charge Collection ◽

Single Event Upset ◽

Single Event ◽

Energetic Ions

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1996 Symposium on VLSI Technology. Digest of Technical PapersLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Widerkehr & Associates

A manufacturable 0.30 μm gate CMOS technology for high speed microprocessors

A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application

Copper interconnection deposition techniques and integration

An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 μm interconnects

A 50 GHz implanted base silicon bipolar technology with 35 GHz static frequency divider

Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs

Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering

NURA: a feasible, gas-dielectric interconnect process

Fully self-aligned 6F/sup 2/ cell technology for low cost 1Gb DRAM

Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

1996 Symposium on VLSI Technology. Digest of Technical Papers
Latest Publications