Single event upset and charge collection measurements using high energy protons and neutrons

1994 ◽  
Vol 41 (6) ◽  
pp. 2203-2209 ◽  
Author(s):  
E. Normand ◽  
D.L. Oberg ◽  
J.L. Wert ◽  
J.D. Ness ◽  
P.P. Majewski ◽  
...  
Keyword(s):  
High Energy ◽  
Charge Collection ◽  
Single Event Upset ◽  
Single Event ◽  
Protons And Neutrons

scholarly journals Influence of Orbital Parameters on SEU Rate of Low-Energy Proton in Nano-SRAM Device

Symmetry ◽  
2020 ◽  
Vol 12 (12) ◽  
pp. 2030
Author(s):  
Bing Ye ◽  
Li-Hua Mo ◽  
Tao Liu ◽  
You-Mei Sun ◽  
Jie Liu
Keyword(s):  
Heavy Ion ◽  
High Energy ◽  
Low Energy ◽  
Single Event Upset ◽  
Single Event ◽  
High Energy Proton ◽  
Orbital Parameters ◽  
Energy Proton ◽  
Orbital Height ◽  
Selection Of

The on-orbit single-event upset (SEU) rate of nanodevices is closely related to the orbital parameters. In this paper, the on-orbit SEU rate (OOSR) induced by a heavy ion (HI), high-energy proton (HEP) and low-energy proton (LEP) for a 65 nm SRAM device is calculated by using the software SPACE RADIATION under different orbits based on the experimental data. The results indicate that the OOSR induced by the HI, HEP and LEP varies with the orbital parameters. In particular, the orbital height, inclination and shieling thickness are the key parameters that affect the contribution of the LEP to the total OOSR. Our results provide guidance for the selection of nanodevices on different orbits.

Simulation of single event upset in semiconductor device induced by high energy neutrons

2014 ◽  
Vol 44 (5) ◽  
pp. 479-485 ◽  
Author(s):  
Wen YIN ◽  
TianJiao LIANG ◽  
ZhiLiang HU ◽  
QuanZhi YU
Keyword(s):  
Semiconductor Device ◽  
High Energy ◽  
Single Event Upset ◽  
Single Event

Charge-Collection and Single-Event Upset Measurements at the ISIS Neutron Source

2008 ◽  
Vol 55 (4) ◽  
pp. 2126-2132 ◽  
Author(s):  
Simon Platt ◽  
ZoltÁn Torok ◽  
Chris D. Frost ◽  
Stuart Ansell
Keyword(s):  
Neutron Source ◽  
Charge Collection ◽  
Single Event Upset ◽  
Single Event

scholarly journals Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

2019 ◽  
Vol 9 (3) ◽  
pp. 21 ◽  
Author(s):  
Satheesh Kumar S ◽  
Kumaravel S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Energy ◽  
Oxide Semiconductor ◽  
High Energy Particle ◽  
Single Event Upset ◽  
Single Event ◽  
Clock Gating

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.

Pulsed laser-induced single event upset and charge collection measurements as a function of optical penetration depth

1998 ◽  
Vol 84 (2) ◽  
pp. 690-703 ◽  
Author(s):  
Joseph S. Melinger ◽  
Dale McMorrow ◽  
A. B. Campbell ◽  
Stephen Buchner ◽  
Lan Hu Tran ◽  
...  
Keyword(s):  
Penetration Depth ◽  
Pulsed Laser ◽  
Charge Collection ◽  
Single Event Upset ◽  
Single Event ◽  
Optical Penetration Depth
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