A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

2001 ◽  
Vol 48 (10) ◽  
pp. 2363-2369 ◽  
Author(s):  
H. Wakabayashi ◽  
Y. Saito ◽  
K. Takeuchi ◽  
T. Mogami ◽  
T. Kunio
Keyword(s):  
Nitrogen Concentration ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

Continuous and Precise Work Function Adjustment for Integratable Dual Metal Gate CMOS Technology Using Hf–Mo Binary Alloys

2005 ◽  
Vol 52 (6) ◽  
pp. 1172-1179 ◽  
Author(s):  
T.-L. Li ◽  
C.-H. Hu ◽  
W.-L. Ho ◽  
H.C.-H. Wang ◽  
C.-Y. Chang
Keyword(s):  
Work Function ◽  
Binary Alloys ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

2001 ◽  
Vol 22 (5) ◽  
pp. 227-229 ◽  
Author(s):  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
P. Ranade ◽  
H. Takeuchi ◽  
K.J. Yang ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectric ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

scholarly journals Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Wu-Te Weng ◽  
Yao-Jen Lee ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Metal Oxide ◽  
Gate Dielectric ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Metal Gates ◽  
Bias Temperature Instability ◽  
Dual Metal

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Metal Wet Etch Process Development for Dual Metal Gate CMOS

2005 ◽  
Vol 8 (12) ◽  
pp. G333 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Joel Barnett ◽  
Jason Saulters ◽  
David Baker ◽  
...  
Keyword(s):  
Process Development ◽  
Metal Gate ◽  
Dual Metal ◽  
Wet Etch

A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology

2011 ◽  
Author(s):  
Min Dai ◽  
Jinping Liu ◽  
Dechao Guo ◽  
Siddarth Krishnan ◽  
Joseph F. Shepard ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Cmos Technology ◽  
Metal Gate

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

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