Metal Wet Etch Process Development for Dual Metal Gate CMOS

2005 ◽  
Vol 8 (12) ◽  
pp. G333 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Joel Barnett ◽  
Jason Saulters ◽  
David Baker ◽  
...  
Keyword(s):  
Process Development ◽  
Metal Gate ◽  
Dual Metal ◽  
Wet Etch

Metal Wet Etch Issues and Effects in Dual Metal Gate Stack Integration

2006 ◽  
Vol 153 (5) ◽  
pp. G389 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Zhibo Zhang ◽  
Baxter F. Womack
Keyword(s):  
Metal Gate ◽  
Gate Stack ◽  
Dual Metal ◽  
Wet Etch

Integration of Dual Metal Gate CMOS on High-k Dielectrics Utilizing a Metal Wet Etch Process

2005 ◽  
Vol 8 (10) ◽  
pp. G271 ◽  
Author(s):  
Zhibo Zhang ◽  
S. C. Song ◽  
Craig Huffman ◽  
Muhammad M. Hussain ◽  
Joel Barnett ◽  
...  
Keyword(s):  
Metal Gate ◽  
High K ◽  
Dual Metal ◽  
Wet Etch

Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

2013 ◽  
Vol 34 (12) ◽  
pp. 1488-1490 ◽  
Author(s):  
Zhaoyun Tang ◽  
Jing Xu ◽  
Hong Yang ◽  
Hushan Cui ◽  
Bo Tang ◽  
...  
Keyword(s):  
Etch Stop ◽  
Etch Stop Layer ◽  
Dual Metal ◽  
Wet Etch

Surface Preparations Impact on 248nm Deep UV Photo Resists Adhesion during a Wet Etch

2012 ◽  
Vol 195 ◽  
pp. 58-61 ◽  
Author(s):  
Mathieu Foucaud ◽  
Philippe Garnier ◽  
Vincent Joseph ◽  
Erwine Pargon ◽  
Névine Rochat ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integration Scheme ◽  
Metal Gate ◽  
Covalent Bonds ◽  
Gate Oxides ◽  
Process Step ◽  
High K ◽  
Lift Off ◽  
Wet Etch

Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.

Effect of Au-Al Dual-Metal Gate on 3D Double-Gate Junctionless Transistor Performance

2021 ◽  
pp. 421-429
Author(s):  
Achinta Baidya ◽  
Rajesh Saha ◽  
Amarnath Gaini ◽  
Chaitali Koley ◽  
Somen Debnath ◽  
...  
Keyword(s):  
Double Gate ◽  
Metal Gate ◽  
Junctionless Transistor ◽  
Dual Metal
Sign in / Sign up

Export Citation Format

Share Document