Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

2001 ◽  
Vol 22 (5) ◽  
pp. 227-229 ◽  
Author(s):  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
P. Ranade ◽  
H. Takeuchi ◽  
K.J. Yang ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectric ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

scholarly journals Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Wu-Te Weng ◽  
Yao-Jen Lee ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Metal Oxide ◽  
Gate Dielectric ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Metal Gates ◽  
Bias Temperature Instability ◽  
Dual Metal

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

Continuous and Precise Work Function Adjustment for Integratable Dual Metal Gate CMOS Technology Using Hf–Mo Binary Alloys

2005 ◽  
Vol 52 (6) ◽  
pp. 1172-1179 ◽  
Author(s):  
T.-L. Li ◽  
C.-H. Hu ◽  
W.-L. Ho ◽  
H.C.-H. Wang ◽  
C.-Y. Chang
Keyword(s):  
Work Function ◽  
Binary Alloys ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

2001 ◽  
Vol 48 (10) ◽  
pp. 2363-2369 ◽  
Author(s):  
H. Wakabayashi ◽  
Y. Saito ◽  
K. Takeuchi ◽  
T. Mogami ◽  
T. Kunio
Keyword(s):  
Nitrogen Concentration ◽  
Cmos Technology ◽  
Metal Gate ◽  
Dual Metal

Compatibility of HfxTayN metal gate electrode with HfOxNy gate dielectric for advanced CMOS technology

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2516-2521
Author(s):  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang
Keyword(s):  
Gate Dielectric ◽  
Cmos Technology ◽  
Gate Electrode ◽  
Metal Gate

Evaluation of Candidate Metals for Dual-Metal Gate CMOS with HfO2 Gate Dielectric

2002 ◽  
Vol 716 ◽  
Author(s):  
S.B. Samavedam ◽  
J.K. Schaeffer ◽  
D.C. Gilmer ◽  
V. Dhandapani ◽  
P.J. Tobin ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Metal Gate ◽  
Mos Capacitors ◽  
Dielectric Thickness ◽  
Metal Gates ◽  
Polysilicon Gate ◽  
Dual Metal ◽  
High Dielectric

AbstractAs the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO2 n-MOSFETs.

Dual-metal gate CMOS with HfO/sub 2/ gate dielectric

2003 ◽  
Author(s):  
S.B. Samavedam ◽  
L.B. La ◽  
J. Smith ◽  
S. Dakshina-Murthy ◽  
E. Luckowski ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Metal Gate ◽  
Dual Metal

Zr Oxide Based Gate Dielectrics with Equivalent SiO2 Thickness of Less than 1.0 nm and Device Integration with Pt Gate Electrode

2000 ◽  
Vol 611 ◽  
Author(s):  
Yanjun Ma ◽  
Yoshi Ono
Keyword(s):  
Gate Dielectric ◽  
Process Integration ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Metal Gate ◽  
Leakage Currents ◽  
Gate Electrodes ◽  
Device Integration ◽  
Dual Metal

ABSTRACTZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.

Sign in / Sign up

Export Citation Format

Share Document