scholarly journals Remote surface roughness scattering in fully depleted silicon-on-insulator devices with high-κ/SiO2 gate stacks

2015 ◽  
Vol 106 (2) ◽  
pp. 023508 ◽  
Author(s):  
Y. M. Niquet ◽  
I. Duchemin ◽  
V.-H. Nguyen ◽  
F. Triozon ◽  
D. Rideau
Keyword(s):  
Surface Roughness ◽  
Silicon On Insulator ◽  
Gate Stacks ◽  
Fully Depleted ◽  
Surface Roughness Scattering

Role of surface-roughness scattering in double gate silicon-on-insulator inversion layers

2001 ◽  
Vol 89 (3) ◽  
pp. 1764 ◽  
Author(s):  
F. Gámiz ◽  
J. B. Roldán ◽  
P. Cartujo-Cassinello ◽  
J. A. López-Villanueva ◽  
P. Cartujo
Keyword(s):  
Surface Roughness ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Surface Roughness Scattering

The effect of surface roughness scattering on hole mobility in double gate silicon-on-insulator devices

2009 ◽  
Vol 106 (2) ◽  
pp. 023705 ◽  
Author(s):  
Luca Donetti ◽  
Francisco Gámiz ◽  
Noel Rodriguez ◽  
Andres Godoy ◽  
Carlos Sampedro
Keyword(s):  
Surface Roughness ◽  
Hole Mobility ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Surface Roughness Scattering ◽  
Effect Of Surface

Surface roughness at the Si–SiO2 interfaces in fully depleted silicon-on-insulator inversion layers

1999 ◽  
Vol 86 (12) ◽  
pp. 6854-6863 ◽  
Author(s):  
F. Gámiz ◽  
J. B. Roldán ◽  
J. A. López-Villanueva ◽  
P. Cartujo-Cassinello ◽  
J. E. Carceller
Keyword(s):  
Surface Roughness ◽  
Silicon On Insulator ◽  
Fully Depleted

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 1101-1104 ◽  
Author(s):  
M.G. Jaikumar ◽  
Shreepad Karmalkar
Keyword(s):  
Surface Roughness ◽  
Measured Data ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Material Parameters ◽  
Velocity Saturation ◽  
Physical Mechanisms ◽  
Surface Roughness Scattering ◽  
Wide Range ◽  
Tcad Simulation

4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.

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