Gate stack insulator breakdown when the interface layer thickness is scaled toward zero

2010 ◽  
Vol 97 (21) ◽  
pp. 213503 ◽  
Author(s):  
Jordi Suñé ◽  
Santi Tous ◽  
Enrique Miranda
Keyword(s):  
Layer Thickness ◽  
Interface Layer ◽  
Gate Stack

Direct LaLuO3/Ge Gate Stack Formation by Interface Layer Scavenging and Subsequent Low Temperature O2 Annealing

2019 ◽  
Vol 33 (3) ◽  
pp. 375-382 ◽  
Author(s):  
Toshiyuki Tabata ◽  
Choong Hyun Lee ◽  
Koji Kita ◽  
Akira Toriumi
Keyword(s):  
Low Temperature ◽  
Interface Layer ◽  
Gate Stack

scholarly journals Impact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective

2021 ◽  
Vol 1070 (1) ◽  
pp. 012081
Author(s):  
Vibhu Goyal ◽  
Shubham Tayal ◽  
Shweta Meena ◽  
Ravi Gupta
Keyword(s):  
Layer Thickness ◽  
Interfacial Layer ◽  
Gate Stack

Determination of interface layer thickness of a pseudo two-phase system by extension of the Debye equation

2001 ◽  
Vol 34 (14) ◽  
pp. 2085-2088 ◽  
Author(s):  
Zhi Hong Li ◽  
Yan Jun Gong ◽  
Min Pu ◽  
Dong Wu ◽  
Yu Han Sun ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Interface Layer ◽  
Phase System ◽  
Two Phase ◽  
Debye Equation

Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET

2018 ◽  
Vol 13 (10) ◽  
pp. 1473-1477 ◽  
Author(s):  
Sanjeev Kumar Sharma ◽  
Jeetendra Singh ◽  
Balwinder Raj ◽  
Mamta Khosla
Keyword(s):  
Layer Thickness ◽  
Barrier Layer ◽  
Significant Variation ◽  
Barrier Thickness ◽  
Gate Stack ◽  
Barrier Layer Thickness ◽  
Nanowire Mosfets ◽  
Silvaco Atlas ◽  
Nanowire Mosfet

In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

Effects of crystallization rates on interface layer thickness of epitaxial HDPE on oriented iPP

1994 ◽  
Vol 29 (7) ◽  
pp. 1773-1780 ◽  
Author(s):  
Shouke Yan ◽  
Jian Lin ◽  
Decai Yang ◽  
J. Petermann
Keyword(s):  
Layer Thickness ◽  
Interface Layer

Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness

2006 ◽  
Vol 27 (7) ◽  
pp. 546-548 ◽  
Author(s):  
B.J. O'Sullivan ◽  
V.S. Kaushik ◽  
L.-A. Ragnarsson ◽  
B. Onsia ◽  
N. Van Hoornick ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Interface Layer ◽  
Device Performance

Controlling of the photosensing properties of Al/DMY/p-Si heterojunctions by the interface layer thickness

2016 ◽  
Vol 221 ◽  
pp. 114-119 ◽  
Author(s):  
A. Gencer Imer ◽  
O. Karaduman ◽  
F. Yakuphanoglu
Keyword(s):  
Layer Thickness ◽  
Interface Layer

Dependence of interface layer thickness in FeCo–Si multilayers on sputtering parameters

2003 ◽  
Vol 444 (1-2) ◽  
pp. 158-164 ◽  
Author(s):  
S.-J. Cho ◽  
Th. Krist ◽  
F. Mezei
Keyword(s):  
Layer Thickness ◽  
Interface Layer
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