Long‐term charge storage in interface states of ZnS MOS capacitors

1975 ◽  
Vol 46 (7) ◽  
pp. 2992-2997 ◽  
Author(s):  
L. G. Walker ◽  
G. W. Pratt Jr.
Keyword(s):  
Interface States ◽  
Charge Storage ◽  
Mos Capacitors

A method for modeling and deciphering the persistent photoconductance and long-term charge storage of ZnO nanorod arrays

Nano Research ◽  
2016 ◽  
Vol 9 (10) ◽  
pp. 2972-3002 ◽  
Author(s):  
Qiang Zhu ◽  
Changsheng Xie ◽  
Huayao Li ◽  
Dawen Zeng
Keyword(s):  
Charge Storage ◽  
Zno Nanorod ◽  
Nanorod Arrays ◽  
Zno Nanorod Arrays

Relationship between trapped holes and interface states in MOS capacitors

1980 ◽  
Vol 36 (7) ◽  
pp. 590-592 ◽  
Author(s):  
Genda Hu ◽  
Walter C. Johnson
Keyword(s):  
Interface States ◽  
Mos Capacitors

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Gate Oxide Long-Term Reliability of 4H-SiC MOS Devices

2010 ◽  
Vol 645-648 ◽  
pp. 805-808 ◽  
Author(s):  
Liang Chun Yu ◽  
Kin P. Cheung ◽  
Greg Dunne ◽  
Kevin Matocha ◽  
John S. Suehle ◽  
...  
Keyword(s):  
High Field ◽  
Field Data ◽  
Gate Oxide ◽  
Early Prediction ◽  
Accelerated Test ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Test Conditions ◽  
Oxide Reliability

Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Long-term charge storage in GaP pn junction capacitors

1993 ◽  
Vol 29 (13) ◽  
pp. 1154 ◽  
Author(s):  
Y. Wang ◽  
J. Ramdani ◽  
Y. He ◽  
S.M. Bedair ◽  
J.A. Cooper ◽  
...  
Keyword(s):  
Charge Storage ◽  
Pn Junction

scholarly journals Creation of Interface States at the Silicon/Silicon Dioxide Interface by UV Light Without Hole Trapping

1989 ◽  
Vol 148 ◽  
Author(s):  
W. K. Schubert ◽  
C. H. Seager ◽  
K. L. Brower
Keyword(s):  
Silicon Dioxide ◽  
Silicon Substrate ◽  
Uv Light ◽  
Interface States ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Hole Trapping ◽  
Creation Rate ◽  
Silicon Silicon

ABSTRACTPhotoinjection of electrons into silicon dioxide in metal-oxide-semiconductor (MOS) capacitors with 3.5 eV light is shown to create interface states with no apparent hole trapping precursor. The creation rate of these interface states depends strongly upon whether injection is from the gate metal or the silicon substrate, and on the forming gas annealing sequence used to passivate growth-induced interface states. A mechanism involving electron-induced release of hydrogen in the oxide is consistent with some aspects of the data.

Interface States in 4H- and 6H-SiC MOS Capacitors: A Comparative Study between Conductance Spectroscopy and Thermal Dielectric Relaxation Current Technique

2009 ◽  
Vol 615-617 ◽  
pp. 497-500 ◽  
Author(s):  
Lars S. Løvlie ◽  
Ioana Pintilie ◽  
S. Kumar C.P. ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson ◽  
...  
Keyword(s):  
Comparative Study ◽  
Dielectric Relaxation ◽  
Cross Section ◽  
Capture Cross Section ◽  
Interface States ◽  
Conduction Band Edge ◽  
Capture Cross ◽  
Mos Capacitors ◽  
Dry Oxidation ◽  
Good Agreement

The purpose of this work is to compare the density of shallow interface states (Dit) at the interface of SiO2/SiC MOS capacitors as deducted by the conductance spectroscopy (CS) and thermally dielectric relaxation current (TDRC) techniques. Both capacitors of 4H- and 6H-SiC (n-type) are investigated, and both ordinary dry oxidation and an improved industrial procedure have been employed. The two techniques are found to give rather good agreement for interface states located ≥0.3 eV below the conduction band edge (Ec) while for more shallow states vastly different distributions of Dit are obtained. Different reasons for these contradictory results are discussed, such as strong temperature and energy dependence of the capture cross section of the shallow interface states.

Sign in / Sign up

Export Citation Format

Share Document