Optical capacitance-voltage characterization of charge traps in the trapping nitride layer of charge trapped flash memory devices

2007 ◽  
Vol 91 (22) ◽  
pp. 223511 ◽  
Author(s):  
Jang Uk. Lee ◽  
Kang Seob Roh ◽  
Gu Cheol Kang ◽  
Seung Hwan Seo ◽  
Kwan Young Kim ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nitride Layer ◽  
Memory Devices ◽  
Capacitance Voltage

Characterization of tunnel-oxide degradation due to plasma field oxide recess in flash memory devices

2012 ◽  
Vol 520 (15) ◽  
pp. 5007-5010 ◽  
Author(s):  
Jeungyun Lee ◽  
Dong-Kwon Kim ◽  
Gyung-Jin Min ◽  
Ilsub Chung
Keyword(s):  
Flash Memory ◽  
Memory Devices ◽  
Oxide Degradation ◽  
Field Oxide

Adaptive Interference Mitigation for Multilevel Flash Memory Devices

2011 ◽  
Vol E94-A (11) ◽  
pp. 2453-2457
Author(s):  
Myeongwoon JEON ◽  
Kyungchul KIM ◽  
Sungkyu CHUNG ◽  
Seungjae CHUNG ◽  
Beomju SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Interference Mitigation ◽  
Memory Devices

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CA07 ◽  
Author(s):  
Bong-Su Jo ◽  
Ho-Jung Kang ◽  
Sung-Min Joe ◽  
Min-Kyu Jeong ◽  
Kyung-Rok Han ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Random Telegraph Noise ◽  
Telegraph Noise
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