Effects of low-temperature postannealing on a n+-p shallow junction fabricated by plasma doping

2005 ◽  
Vol 86 (19) ◽  
pp. 193503 ◽  
Author(s):  
Sungkweon Baek ◽  
Hyunsang Hwang ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Jong-Heon Yang ◽  
...  
1995 ◽  
Vol 396 ◽  
Author(s):  
Shu Qin ◽  
James D. Bernstein ◽  
Chung Chan

AbstractHydrogen etching effects in plasma ion implantation (PII) doping processes alter device structure and implant dopant profile and reduce the retained implant dose. This has particular relevance to the shallow junction devices of ultra large scale integrated circuits (ULSI). Hydrogen etching of semiconductor materials including Si, poly-Si, SiO2, Al, and photoresist films have been investigated. The effects of varying different PII process parameters are presented. The experimental data show that the spontaneous etching by hydrogen radicals enhanced by ion bombardment is responsible for the etching phenomena. A computer simulation is used to predict the as-implanted impurity profile and the retained implant dose for a shallow junction doping when the etching effect is considered.


1997 ◽  
Vol 70 (13) ◽  
pp. 1700-1702 ◽  
Author(s):  
R. Singh ◽  
K. C. Cherukuri ◽  
L. Vedula ◽  
A. Rohatgi ◽  
S. Narayanan

Author(s):  
B. Mizuno ◽  
K. Okashita ◽  
K. Nakamoto ◽  
C.G. Jin ◽  
Y. Sasaki ◽  
...  

2005 ◽  
Vol 864 ◽  
Author(s):  
Jong-Heon Yang ◽  
In-Bok Baek ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Sungkweon Baek ◽  
...  

AbstractWe fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350··, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices.


2000 ◽  
Vol 610 ◽  
Author(s):  
Jian-Yue Jina ◽  
Irene Rusakova ◽  
Qinmian Li ◽  
Jiarui Liu ◽  
Wei-Kan Chu

AbstractLow temperature annealing combined with pre-damage (or preamorphization) implantation is a very promising method to overcome the activation barrier in ultra-shallow junction formation. We have made a 32 nm p+/n junction with sheet resistance of 290 /sq. using 20 keV 4×1014 Ω/cm2 Si followed by 2 keV 1×1015 at./cm2 B implantation and 10 minutes 550 °C annealing. This paper studies the boron activation mechanism during low temperature annealing. The result shows that placing B profile in the vacancyrich region has much better boron activation than placing B profile in interstitial-rich region or without pre-damage. It also shows that a significant portion of boron is in substitutional positions before annealing. The amount of substitutional boron is correlated to the amount of vacancies (damage) by the pre-damage Si implantation. The result supports our speculation that vacancy enhances boron activation.


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