Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET

2018 ◽  
Vol 13 (5) ◽  
pp. 690-694 ◽  
Author(s):  
Kalyan Biswas ◽  
Angsuman Sarkar ◽  
Chandan Kumar Sarkar
Keyword(s):  
Double Gate ◽  
Circuit Performance ◽  
Indium Concentration

scholarly journals Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Seong-Joo Han ◽  
Joon-kyu Han ◽  
Myung-Su Kim ◽  
Gyeong-Jun Yun ◽  
Ji-Man Yu ◽  
...  
Keyword(s):  
Silicon Nanowire ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Ternary Logic ◽  
Promising Candidate ◽  
Circuit Performance ◽  
Cmos Compatibility ◽  
Silvaco Atlas ◽  
Power Delay Product ◽  
Tcad Simulations

AbstractA ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

Circuit performance of double-gate SOI CMOS

2004 ◽  
Author(s):  
C.-H. Lin ◽  
P. Su ◽  
Y. Tau ◽  
X. Xi ◽  
J. He ◽  
...  
Keyword(s):  
Double Gate ◽  
Circuit Performance ◽  
Soi Cmos

Implementation of double-gate junctionless transistor and its circuit performance analysis

2016 ◽  
Author(s):  
Rhushikesh K. Joshi ◽  
T. V. Arjun ◽  
S. Ahish ◽  
Dheeraj Sharma ◽  
M. H. Vasantha ◽  
...  
Keyword(s):  
Performance Analysis ◽  
Double Gate ◽  
Circuit Performance ◽  
Junctionless Transistor

Predicting Analog Circuit Performance Based on Importance of Uncertainties

2010 ◽  
Vol E93-C (6) ◽  
pp. 893-904
Author(s):  
Jin SUN ◽  
Kiran POTLURI ◽  
Janet M. WANG
Keyword(s):  
Analog Circuit ◽  
Circuit Performance
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