Fabrication of a m.o.s.f.e.t. with ‘spoxide’ as the gate dielectric having low interface state density

1978 ◽  
Vol 14 (24) ◽  
pp. 754
Author(s):  
Utpal Kumar Chakrabarti
Keyword(s):  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Interface State Density

Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer

2019 ◽  
Vol 40 (2) ◽  
pp. 174-176
Author(s):  
Yi-He Tsai ◽  
Chen-Han Chou ◽  
Yun-Yan Chung ◽  
Wen-Kuan Yeh ◽  
Yu-Hsien Lin ◽  
...  
Keyword(s):  
Interfacial Layer ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Interface State Density

Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC

2020 ◽  
Vol 1004 ◽  
pp. 535-540
Author(s):  
Min Who Lim ◽  
Tomasz Sledziewski ◽  
Mathias Rommel ◽  
Tobias Erlbacher ◽  
Hong Ki Kim ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Breakdown Strength ◽  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Interface Quality ◽  
Post Deposition ◽  
Interfacial Oxidation

In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Interface Passivation in Amorphous Silicon TFTs by Various Gate Dielectric Materials

1987 ◽  
Vol 95 ◽  
Author(s):  
R. C. Fryea ◽  
C. C. Wong ◽  
C. Kornfeld
Keyword(s):  
Amorphous Silicon ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Materials ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Photothermal Deflection Spectroscopy ◽  
Device Stability ◽  
Interface Passivation

AbstractWe have used photothermal deflection spectroscopy to examine deep gap absorption in amorphous silicon films deposited on silicon oxide and silicon nitride. Variations in the interface state density deduced from PDS correlate well with the performance characteristics of thin-film transistors. We have demonstrated processes which degrade the interfacial abruptness also increase the interface state density. In transistors this leads to a degradation in device stability. We found devices with oxide gates to be more stable and show lower interface state density than devices with nitride gates for a specific set of deposition conditions. The correspondence between deep gap absorption and transistor characteristics shows that PDS is a valuable technique for characterizing and optimizing fabrication processes.

Interface-State-Density Evaluation of p-type and n-type Ge/GeNx Structures by Conductance Technique

2013 ◽  
Vol 133 (7) ◽  
pp. 1279-1284
Author(s):  
Takuro Iwasaki ◽  
Toshiro Ono ◽  
Yohei Otani ◽  
Yukio Fukuda ◽  
Hiroshi Okamoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Conductance Technique ◽  
Density Evaluation ◽  
P Type

Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Wafer Surface ◽  
Oxide Charge ◽  
Contact Test ◽  
Deposition Power ◽  
Oxide Deposition

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

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