Lowering interface state density in carbon nanotube thin film transistors through using stacked Y2O3/HfO2 gate dielectric

2018 ◽  
Vol 113 (8) ◽  
pp. 083105 ◽  
Author(s):  
Lin Xu ◽  
Ningfei Gao ◽  
Zhiyong Zhang ◽  
Lian-Mao Peng
Keyword(s):  
Thin Film ◽  
Carbon Nanotube ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Interface State Density

Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors

1998 ◽  
Vol 84 (4) ◽  
pp. 2341-2348 ◽  
Author(s):  
L. Mariucci ◽  
G. Fortunato ◽  
R. Carluccio ◽  
A. Pecora ◽  
S. Giovannini ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Silicon Thin Film ◽  
Hot Carrier

Investigation of the off-current in amorphous silicon thin film transistors for SiO2 and SiNx. gate insulators

1996 ◽  
Vol 424 ◽  
Author(s):  
Jeong Hyun Kim ◽  
Woong Sik Choi ◽  
Chan Hee Hong ◽  
Hoe Sup Soh
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Defect States ◽  
Silicon Thin Film ◽  
Pressure Chemical

AbstractThe off current behavior of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) with an atmospheric pressure chemical vapor deposition (APCVD) silicon dioxide (SiO2) gate insulator were investigated at negative gate voltages. The a-Si:H TFT with SiO2 gate insulator has small off currents and large activation energy (Ea) of the off current compared to the a-Si:H TFT with SiNx gate insulator. The holes induced in the channel by negative gate voltage seem to be trapped in the defect states near the a-Si:H/SiO2 interface. The interface state density in the lower half of the band gap of a-Si:H/SiO2 appears to be much higher than that for a-Si:H/SiNx.

Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer

2019 ◽  
Vol 40 (2) ◽  
pp. 174-176
Author(s):  
Yi-He Tsai ◽  
Chen-Han Chou ◽  
Yun-Yan Chung ◽  
Wen-Kuan Yeh ◽  
Yu-Hsien Lin ◽  
...  
Keyword(s):  
Interfacial Layer ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Interface State Density

Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC

2020 ◽  
Vol 1004 ◽  
pp. 535-540
Author(s):  
Min Who Lim ◽  
Tomasz Sledziewski ◽  
Mathias Rommel ◽  
Tobias Erlbacher ◽  
Hong Ki Kim ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Breakdown Strength ◽  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Interface Quality ◽  
Post Deposition ◽  
Interfacial Oxidation

In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

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