2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

Xiao‐Peng Yu; Yun Fang; Zheng Shi

doi:10.1049/el.2016.1232

2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

Electronics Letters ◽

10.1049/el.2016.1232 ◽

2016 ◽

Vol 52 (14) ◽

pp. 1261-1262 ◽

Cited By ~ 2

Author(s):

Xiao‐Peng Yu ◽

Yun Fang ◽

Zheng Shi

Keyword(s):

Duty Cycle ◽

Clock Generator ◽

Phase Clock ◽

Multi Phase

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A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS

Integration ◽

10.1016/j.vlsi.2018.05.011 ◽

2018 ◽

Vol 63 ◽

pp. 87-92 ◽

Cited By ~ 1

Author(s):

Yun Fang ◽

Xiao-Peng Yu ◽

Zheng Shi ◽

Kiat Seng Yeo

Keyword(s):

Duty Cycle ◽

Clock Generator ◽

Phase Clock ◽

Multi Phase

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CMOS digital duty cycle correction circuit for multi-phase clock

Electronics Letters ◽

10.1049/el:20030908 ◽

2003 ◽

Vol 39 (19) ◽

pp. 1383 ◽

Cited By ~ 26

Author(s):

Y.C. Jang ◽

S.J. Bae ◽

H.J. Park

Keyword(s):

Duty Cycle ◽

Phase Clock ◽

Multi Phase

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A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) ◽

10.1109/isscc.2001.912690 ◽

2002 ◽

Author(s):

Lin Wu ◽

W.C. Black

Keyword(s):

Clock Generator ◽

Low Jitter ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8126559 ◽

2017 ◽

Author(s):

Xinquan Lai ◽

Kai Zhang ◽

Chen Liu ◽

Yuheng Wang ◽

Longjie Zhong ◽

...

Keyword(s):

High Accuracy ◽

Switched Capacitor ◽

Readout Circuit ◽

Clock Generator ◽

Fully Differential ◽

Phase Clock ◽

Multi Phase

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An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

IEICE Transactions on Electronics ◽

10.1093/ietele/e90-c.6.1156 ◽

2007 ◽

Vol E90-C (6) ◽

pp. 1156-1164 ◽

Cited By ~ 4

Author(s):

Y.-C. JANG ◽

J.-H. BAE ◽

S.-H. PARK ◽

J.-Y. SIM ◽

H.-J. PARK

Keyword(s):

Clock Generator ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5117670 ◽

2009 ◽

Cited By ~ 2

Author(s):

Dongsuk Shin ◽

Jabeom Koo ◽

Won-Joo Yun ◽

Young Jung Choi ◽

Chulwoo Kim

Keyword(s):

Clock Generator ◽

Digital Converter ◽

Time To Digital Converter ◽

Phase Clock ◽

Multi Phase

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A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET

2019 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2019.8780177 ◽

2019 ◽

Author(s):

Sanquan Song ◽

John Poulton ◽

Xi Chen ◽

Brian Zimmer ◽

Stephen G. Tell ◽

...

Keyword(s):

High Speed ◽

Clock Generator ◽

Phase Clock ◽

Multi Phase

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An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021295 ◽

2014 ◽

Author(s):

Jifang Wu ◽

Fule Li ◽

Chun Zhang

Keyword(s):

Sar Adc ◽

Ring Oscillator ◽

Clock Generator ◽

Phase Clock ◽

Asynchronous Sar ◽

Multi Phase

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Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance

IEEE Custom Integrated Circuits Conference 2006 ◽

10.1109/cicc.2006.320967 ◽

2006 ◽

Cited By ~ 5

Author(s):

Amber Han-yuan Tan ◽

Gu-yeon Wei

Keyword(s):

Clock Generator ◽

Adaptive Bandwidth ◽

Phase Clock ◽

Multi Phase

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Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator

IEEE Custom Integrated Circuits Conference 2006 ◽

10.1109/cicc.2006.320986 ◽

2006 ◽

Cited By ~ 7

Author(s):

Amber Tan ◽

Gu-yeon Wei

Keyword(s):

Phase Mismatch ◽

Clock Generator ◽

Mismatch Detection ◽

Phase Clock ◽

Multi Phase

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2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS

CMOS digital duty cycle correction circuit for multi-phase clock

A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET

An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator

Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance

Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS