CMOS digital duty cycle correction circuit for multi-phase clock

Y.C. Jang; S.J. Bae; H.J. Park

doi:10.1049/el:20030908

CMOS digital duty cycle correction circuit for multi-phase clock

Electronics Letters ◽

10.1049/el:20030908 ◽

2003 ◽

Vol 39 (19) ◽

pp. 1383 ◽

Cited By ~ 26

Author(s):

Y.C. Jang ◽

S.J. Bae ◽

H.J. Park

Keyword(s):

Duty Cycle ◽

Phase Clock ◽

Multi Phase

Download Full-text

2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

Electronics Letters ◽

10.1049/el.2016.1232 ◽

2016 ◽

Vol 52 (14) ◽

pp. 1261-1262 ◽

Cited By ~ 2

Author(s):

Xiao‐Peng Yu ◽

Yun Fang ◽

Zheng Shi

Keyword(s):

Duty Cycle ◽

Clock Generator ◽

Phase Clock ◽

Multi Phase

Download Full-text

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS

Integration ◽

10.1016/j.vlsi.2018.05.011 ◽

2018 ◽

Vol 63 ◽

pp. 87-92 ◽

Cited By ~ 1

Author(s):

Yun Fang ◽

Xiao-Peng Yu ◽

Zheng Shi ◽

Kiat Seng Yeo

Keyword(s):

Duty Cycle ◽

Clock Generator ◽

Phase Clock ◽

Multi Phase

Download Full-text

A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) ◽

10.1109/isscc.2001.912690 ◽

2002 ◽

Author(s):

Lin Wu ◽

W.C. Black

Keyword(s):

Clock Generator ◽

Low Jitter ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

Download Full-text

Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits

2012 IEEE 42nd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2012.30 ◽

2012 ◽

Author(s):

R. P. Menon ◽

M. A. Thornton

Keyword(s):

Integrated Circuits ◽

High Performance ◽

Phase Clock ◽

Multi Phase

Download Full-text

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_18 ◽

2019 ◽

pp. 202-214

Author(s):

Raviteja Kammari ◽

Vijaya Sankara Rao Pasupureddi

Keyword(s):

Delay Element ◽

Power Efficient ◽

Clock Generation ◽

Efficient Charge ◽

Phase Clock ◽

Multi Phase ◽

Widely Linear

Download Full-text

A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8126559 ◽

2017 ◽

Author(s):

Xinquan Lai ◽

Kai Zhang ◽

Chen Liu ◽

Yuheng Wang ◽

Longjie Zhong ◽

...

Keyword(s):

High Accuracy ◽

Switched Capacitor ◽

Readout Circuit ◽

Clock Generator ◽

Fully Differential ◽

Phase Clock ◽

Multi Phase

Download Full-text

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

IEICE Transactions on Electronics ◽

10.1093/ietele/e90-c.6.1156 ◽

2007 ◽

Vol E90-C (6) ◽

pp. 1156-1164 ◽

Cited By ~ 4

Author(s):

Y.-C. JANG ◽

J.-H. BAE ◽

S.-H. PARK ◽

J.-Y. SIM ◽

H.-J. PARK

Keyword(s):

Clock Generator ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

Download Full-text

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.4.773 ◽

2005 ◽

Vol E88-C (4) ◽

pp. 773-777 ◽

Cited By ~ 11

Author(s):

J.-J. NAM

Keyword(s):

Duty Cycle ◽

Digital Cmos ◽

Multi Phase

Download Full-text

A 1.0Gb/s/ch Clock-shared differential signaling(CSDS) Tx using termination resistance tuning and multi-phase clock spreading for EMI reduction

2010 IEEE Asian Solid-State Circuits Conference ◽

10.1109/asscc.2010.5716567 ◽

2010 ◽

Author(s):

Kyoung-Hoi Koo ◽

Jaejin Park ◽

Donguk Park ◽

Eon-Guk Kim ◽

Seungho Lee ◽

...

Keyword(s):

Differential Signaling ◽

Phase Clock ◽

Multi Phase ◽

Emi Reduction

Download Full-text

A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array

2012 18th IEEE-NPSS Real Time Conference ◽

10.1109/rtc.2012.6418217 ◽

2012 ◽

Cited By ~ 5

Author(s):

Zhoujiancheng Yin ◽

Shubin Liu ◽

Xinjun Hao ◽

Shanshan Gao ◽

Qi An

Keyword(s):

High Resolution ◽

Field Programmable Gate Array ◽

Digital Converter ◽

Resolution Time ◽

Time To Digital Converter ◽

Field Programmable ◽

Phase Clock ◽

Gate Array ◽

Multi Phase

Download Full-text

CMOS digital duty cycle correction circuit for multi-phase clock

2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS

A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

A 1.0Gb/s/ch Clock-shared differential signaling(CSDS) Tx using termination resistance tuning and multi-phase clock spreading for EMI reduction

A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS