An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

Design of double ring lock ring in extensible frequency clock generator chip

With the continuous development of computer technology and the continuous improvement of interface data rate, the clock frequency has reached the demand of several gigahertz, which makes the electromagnetic interference problem very serious. Spread spectrum clock is an effective method to reduce electromagnetic interference of digital chips. Therefore, this paper designs a double-loop phase-locked loop that can spread spectrum and has strong anti-electromagnetic noise interference ability. The designed dual-loop phase-locked loop can be used in the clock generator chip. The overall structure of the circuit consists of a main loop and a secondary loop. The main loop is an adjustable phase-locked loop circuit that can provide an output with a center frequency of 500MHz. The secondary loop can realize the spread spectrum function by charging and discharging the filter capacitor of the main loop loop, and at the same time, the spreading depth can be set by the feedback based on the frequency division. The dual-loop phase-locked loop designed in this paper has a good effect in spread spectrum and anti-electromagnetic interference noise.

EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret.

A Regulated Pulse Current Driver with Spread Spectrum Clock Generator †

This paper presents a regulated pulse current driver with a spread spectrum clock generator (SSCG) to lower the electromagnetic interference (EMI) effect. An SSCG is used and implemented by applying a triangular wave to modulate a voltage-controlled oscillator (VCO). The results show a 7 dBm reduction in the peak power level with a frequency deviation of 10%, demonstrating that the dominate harmonic is spread and distributed to adjacent frequencies, and the magnitude of harmonics is significantly reduced. The results demonstrate that the driver with a spread spectrum clock generator would help to reduce interference in sensitive electronic components and be suitable for portable consumer electronics applications.

A Reference-Sampling Based Calibration-Free Fractional-N PLL with A PI-Linked Sampling Clock Generator

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.