HfO2/HfS2 hybrid heterostructure fabricated via controllable chemical conversion of two-dimensional HfS2

Nanoscale ◽  
2018 ◽  
Vol 10 (39) ◽  
pp. 18758-18766 ◽  
Author(s):  
Shen Lai ◽  
Seongjae Byeon ◽  
Sung Kyu Jang ◽  
Juho Lee ◽  
Byoung Hun Lee ◽  
...  
Keyword(s):  
Van Der Waals ◽  
Chemical Conversion ◽  
Native Oxide ◽  
Two Dimensional ◽  
Plasma Oxidation ◽  
High K ◽  
High K Dielectric

We demonstrate that HfO2, a high-K dielectric, can be prepared on the top surface of 2D HfS2 through plasma oxidation, which results in a heterostructure composed of a 2D van der Waals semiconductor and its insulating native oxide.

scholarly journals The integration of high-k dielectric on two-dimensional crystals by atomic layer deposition

2012 ◽  
Vol 100 (15) ◽  
pp. 152115 ◽  
Author(s):  
Han Liu ◽  
Kun Xu ◽  
Xujie Zhang ◽  
Peide D. Ye
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Two Dimensional ◽  
Layer Deposition ◽  
High K ◽  
High K Dielectric

scholarly journals Two-Dimensional Covalent Crystals by Chemical Conversion of Thin van der Waals Materials

Nano Letters ◽  
2019 ◽  
Vol 19 (9) ◽  
pp. 6475-6481 ◽  
Author(s):  
Vishnu Sreepal ◽  
Mehmet Yagmurcukardes ◽  
Kalangi S. Vasu ◽  
Daniel J. Kelly ◽  
Sarah F. R. Taylor ◽  
...  
Keyword(s):  
Van Der Waals ◽  
Chemical Conversion ◽  
Two Dimensional ◽  
Van Der Waals Materials

Photo-oxidized HfS2 - An embeddable and writable high-k dielectric for flexible Van der Waals nano-electronics

2018 ◽  
Author(s):  
Namphung Peimyoo ◽  
Jake Mehew ◽  
Matt D. Barnes ◽  
Adolfo De Sanctis ◽  
Iddo Amit ◽  
...  
Keyword(s):  
Van Der Waals ◽  
High K ◽  
High K Dielectric

scholarly journals Laser-writable high-k dielectric for van der Waals nanoelectronics

2019 ◽  
Vol 5 (1) ◽  
pp. eaau0906 ◽  
Author(s):  
N. Peimyoo ◽  
M. D. Barnes ◽  
J. D. Mehew ◽  
A. De Sanctis ◽  
I. Amit ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Van Der Waals ◽  
Van Der Waals Heterostructures ◽  
Electrically Conductive ◽  
Light Emitting ◽  
High K ◽  
Two Dimensional Materials ◽  
High K Dielectric ◽  
Silicon Based

Similar to silicon-based semiconductor devices, van der Waals heterostructures require integration with high-koxides. Here, we demonstrate a method to embed and pattern a multifunctional few-nanometer-thick high-koxide within various van der Waals devices without degrading the properties of the neighboring two-dimensional materials. This transformation allows for the creation of several fundamental nanoelectronic and optoelectronic devices, including flexible Schottky barrier field-effect transistors, dual-gated graphene transistors, and vertical light-emitting/detecting tunneling transistors. Furthermore, upon dielectric breakdown, electrically conductive filaments are formed. This filamentation process can be used to electrically contact encapsulated conductive materials. Careful control of the filamentation process also allows for reversible switching memories. This nondestructive embedding of a high-koxide within complex van der Waals heterostructures could play an important role in future flexible multifunctional van der Waals devices.

Extending the Use of NO Dielectrics for DRAM by Ultrathin Silicon Nitride RTCVD with In Situ Ammonia and Hydrogen Pre-Deposition Surface Conditioning

1997 ◽  
Vol 470 ◽  
Author(s):  
Paul A. Tiner ◽  
Rajesh B. Khamankar ◽  
Clark D. Johnston ◽  
Song C. Park ◽  
Michael F. Pas ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Leakage Current ◽  
Dielectric Films ◽  
Native Oxide ◽  
Surface Conditioning ◽  
Deposition Surface ◽  
High K ◽  
Storage Node ◽  
High K Dielectric

ABSTRACTThe use of thin nitride/oxide (NO) stacked dielectrics is common in DRAM storage node structures today. The cell capacitance can be increased without increasing the cell plate area by decreasing the thickness of the dielectric. Combinations of novel storage node structures, textured electrode surfaces, and very thin NO films (equivalent oxide thickness equal <30 Angstroms) are being characterized for use in 256 Mb and 1 Gb DRAM devices as an alternative to premature use of high k dielectric materials. However, the native oxide formed on the surface of the polysilicon bottom electrode prior to dielectric nitride deposition in a standard LPCVD furnace reactor causes the leakage current and reliability properties of the dielectric to degrade for very thin films. Using a vacuum load-locked RTCVD single-wafer reactor with appropriate in situ ammonia and hydrogen pre-deposition surface conditioning, the native oxide can be eliminated and very thin nitride films of much higher quality can be deposited. A comparison between standard batch LPCVD processing and single-wafer RTCVD for silicon nitride deposition has been done and electrical characteristics (including leakage current and time dependent dielectric breakdown) of the films have been measured. These results indicate that use of NO dielectric films may be extended 1–2 more generations of DRAM devices. This will allow more time for improving the quality of high k dielectric films.

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

2017 ◽  
Vol 26 (01n02) ◽  
pp. 1740003 ◽  
Author(s):  
Henry H. Radamson ◽  
Jun Luo ◽  
Changliang Qin ◽  
Huaxiang Yin ◽  
Huilong Zhu ◽  
...  
Keyword(s):  
Boron Concentration ◽  
Atomic Layer ◽  
Native Oxide ◽  
Electrical Characteristics ◽  
Metal Gate ◽  
Layer Deposition ◽  
High K ◽  
Series Of Experiments ◽  
High K Dielectric

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm−3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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