Extending the Use of NO Dielectrics for DRAM by Ultrathin Silicon Nitride RTCVD with In Situ Ammonia and Hydrogen Pre-Deposition Surface Conditioning

1997 ◽  
Vol 470 ◽  
Author(s):  
Paul A. Tiner ◽  
Rajesh B. Khamankar ◽  
Clark D. Johnston ◽  
Song C. Park ◽  
Michael F. Pas ◽  
...  

ABSTRACTThe use of thin nitride/oxide (NO) stacked dielectrics is common in DRAM storage node structures today. The cell capacitance can be increased without increasing the cell plate area by decreasing the thickness of the dielectric. Combinations of novel storage node structures, textured electrode surfaces, and very thin NO films (equivalent oxide thickness equal <30 Angstroms) are being characterized for use in 256 Mb and 1 Gb DRAM devices as an alternative to premature use of high k dielectric materials. However, the native oxide formed on the surface of the polysilicon bottom electrode prior to dielectric nitride deposition in a standard LPCVD furnace reactor causes the leakage current and reliability properties of the dielectric to degrade for very thin films. Using a vacuum load-locked RTCVD single-wafer reactor with appropriate in situ ammonia and hydrogen pre-deposition surface conditioning, the native oxide can be eliminated and very thin nitride films of much higher quality can be deposited. A comparison between standard batch LPCVD processing and single-wafer RTCVD for silicon nitride deposition has been done and electrical characteristics (including leakage current and time dependent dielectric breakdown) of the films have been measured. These results indicate that use of NO dielectric films may be extended 1–2 more generations of DRAM devices. This will allow more time for improving the quality of high k dielectric films.

2002 ◽  
Vol 738 ◽  
Author(s):  
Xiang-Dong Wang ◽  
Joe Kulik ◽  
N. V. Edwards ◽  
S. B. Samavedam ◽  
Shifeng Lu

ABSTRACTIn this paper, we report the leakage current characterization of HfO2 high-k dielectric thin films by using tunneling AFM, which utilizes a conducting AFM probe to detect current passing through the sample and the probe while simultaneously acquiring a topographic image. We have studied tunneling current behavior of HfO2 films by characterizing the hot spots, which are characterized by excessive local leakage current, as well as the overall current distribution. Tunneling AFM results show sensitive dependence of tunneling current with variation of film thickness. The current distribution can be described approximately by a log-normal distribution, which is consistent with the characteristics of the thickness variation. Furthermore, the film structure and thickness were also characterized with TEM and spectroscopic ellipsometry.


2017 ◽  
Vol 26 (01n02) ◽  
pp. 1740003 ◽  
Author(s):  
Henry H. Radamson ◽  
Jun Luo ◽  
Changliang Qin ◽  
Huaxiang Yin ◽  
Huilong Zhu ◽  
...  

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm−3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.


2016 ◽  
Vol 52 ◽  
pp. 161-167 ◽  
Author(s):  
Igor V. Kotelnikov ◽  
Andrey G. Altynnikov ◽  
Anatoly Konstantinovich Mikhailov ◽  
Valentina V. Medvedeva ◽  
Andrey Kozyrev

2004 ◽  
Vol 13 (1-3) ◽  
pp. 117-120 ◽  
Author(s):  
Simon D. Elliott ◽  
Henry P. Pinto

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000072-000077
Author(s):  
Minoru Osada ◽  
Takayoshi Sasaki

We report on a bottom-up manufacturing for high-k dielectric films using a novel nanomaterial, namely, a perovskite nanosheet (LaNb2O7) derived from a layered perovskite by exfoliation. Solution-based layer-by-layer assembly of perovskite nanosheets is effective for room-temperature fabrication of high-k nanocapacitors, which are directly assembled on a SrRuO3 bottom electrode with an atomically sharp interface. These nanocapacitors exhibit high dielectric constants (k &gt; 50) for thickness down to 5 nm while eliminating problems resulting from the size effect. We also investigate dielectric properties of perovskite nanosheets with different compositions (LaNb2O7, La0.95Eu0.05Nb2O7, and Eu0.56Ta2O7) in order to study the influence of A- and B-site modifications on dielectric properties.


2007 ◽  
Vol 134 ◽  
pp. 379-382
Author(s):  
Claire Therese Richard ◽  
D. Benoit ◽  
S. Cremer ◽  
L. Dubost ◽  
B. Iteprat ◽  
...  

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.


2010 ◽  
Vol 1252 ◽  
Author(s):  
Sahar Sahhaf ◽  
Robin Degraeve ◽  
Mohammed Zahid ◽  
Guido Groeseneken

AbstractIn this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.


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