Memory devices based on functionalized copolymers exhibiting a linear dependence of switch threshold voltage with the pendant nitro-azobenzene moiety content change

2012 ◽  
Vol 22 (37) ◽  
pp. 19957 ◽  
Author(s):  
Naiyong Fan ◽  
Haifeng Liu ◽  
Qianhao Zhou ◽  
Hao Zhuang ◽  
Yang Li ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Linear Dependence ◽  
Memory Devices ◽  
Content Change ◽  
Azobenzene Moiety

scholarly journals Electrode buffer layers producing high performance nonvolatile organic write-once-read-many-times memory devices

RSC Advances ◽  
2017 ◽  
Vol 7 (22) ◽  
pp. 13171-13176 ◽  
Author(s):  
Zhiguo Kong ◽  
Dongxue Liu ◽  
Jinghan He ◽  
Xiuyan Wang
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Memory Device ◽  
Buffer Layers ◽  
Memory Devices

CuI and Bphen buffer layers result in decreased switch threshold voltage and an increased ON/OFF ratio of an organic WORM memory device.

Future Silicon Nanocrystal Nonvolatile Memory Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Michele L. Ostraat ◽  
Jan W. De Blauwe
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Charge Storage ◽  
Memory Devices ◽  
Two Stage ◽  
Nanocrystal Memory

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts > 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.

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