Application of a negative sweep voltage to control gate of fresh flash memory devices to facilitate threshold voltage test measurement

2002 ◽  
Author(s):  
C.L. Cha ◽  
E.F. Chor ◽  
H. Gong ◽  
T.H. Teo ◽  
A.Q. Zhang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Memory Devices ◽  
Test Measurement ◽  
Sweep Voltage

Future Silicon Nanocrystal Nonvolatile Memory Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Michele L. Ostraat ◽  
Jan W. De Blauwe
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Charge Storage ◽  
Memory Devices ◽  
Two Stage ◽  
Nanocrystal Memory

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts > 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.

Efficient flash memory devices based on non-conjugated ferrocene-containing copolymers

2018 ◽  
Vol 6 (42) ◽  
pp. 11348-11355 ◽  
Author(s):  
Jing Xiang ◽  
Xiangling Li ◽  
Yun Ma ◽  
Qiang Zhao ◽  
Cheuk-Lam Ho ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Memory Devices ◽  
Pendant Group ◽  
Current Ratio ◽  
Low Threshold

Non-conjugated ferrocene-containing copolymers FcCP1−FcCP3 with a triphenylamine, benzothiazole or phenothiazine pendant group exhibit flash memory behaviour with a bistable conductive process. Among them, FcCP1 showed a large ON/OFF current ratio of 103 to 104 and a low threshold voltage of −0.6 V.

Adaptive Interference Mitigation for Multilevel Flash Memory Devices

2011 ◽  
Vol E94-A (11) ◽  
pp. 2453-2457
Author(s):  
Myeongwoon JEON ◽  
Kyungchul KIM ◽  
Sungkyu CHUNG ◽  
Seungjae CHUNG ◽  
Beomju SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Interference Mitigation ◽  
Memory Devices
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