Design of Nanoporous Polyarylene Polymers for Use as Low-k Dielectrics in Microelectronic Devices

2004 ◽  
pp. 187-198 ◽  
Author(s):  
H. Craig Silvis ◽  
Kevin J. Bouck ◽  
James P. Godschalx ◽  
Q. Jason Niu ◽  
Michael J. Radler ◽  
...  
Keyword(s):  
Microelectronic Devices ◽  
Low K

Top down nano technologies in surface modification of materials

Open Physics ◽  
2011 ◽  
Vol 9 (2) ◽  
Author(s):  
Branislav Radjenović ◽  
Marija Radmilović-Radjenović
Keyword(s):  
Surface Modification ◽  
Three Dimensional ◽  
Wet Etching ◽  
Plasma Reactors ◽  
Top Down ◽  
Isotropic Etching ◽  
Microelectronic Devices ◽  
Etching Profile ◽  
Simulation Results ◽  
Low K

AbstractThis article contains a broad overview of etch process as one of the most important top-down technologies widely used in semiconductor manufacturing and surface modification of nanostructures. In plasma etching process, the complexity comes from the introduction of new materials and from the constant reduction in dimensions of the structures in microelectronics. The emphasis was made on two types of etching processes: dry etching and wet etching illustrated by three dimensional (3D) simulation results for the etching profile evolution based on the level set method. The etching of low-k dielectrics has been demonstrated via modelling the porous materials. Finally, simulation results for the roughness formation during isotropic etching of nanocomposite materials as well as smoothing of the homogeneous materials have also been shown and analyzed. Simulation results, presented here, indicate that with shrinking microelectronic devices, plasma and wet etching interpretative and predictive modeling and simulation have become increasingly more attractive as a tool for design, control and optimization of plasma reactors.

Structural reliability evaluation of low-k nanoporous dielectric interlayers integrated into microelectronic devices

RSC Advances ◽  
2015 ◽  
Vol 5 (106) ◽  
pp. 87084-87089 ◽  
Author(s):  
Kyuyoung Heo ◽  
Brian J. Ree ◽  
Kyeung-Keun Choi ◽  
Moonhor Ree
Keyword(s):  
Thermal Annealing ◽  
Chemical Mechanical Polishing ◽  
Multilayer Structure ◽  
Structural Reliability ◽  
Reliability Assessment ◽  
Reliability Evaluation ◽  
Mechanical Polishing ◽  
Microelectronic Devices ◽  
Low K

Structural reliability assessment on the integration of low-k nanoporous dielectrics into a multilayer structure, involving capping, chemical mechanical polishing, post-cleaning, and thermal annealing processes, was successfully demonstrated in a nondestructive manner.

Reliability Analysis of Ultra-Low-K Large-Die Package and Wire Bond Chip Package on Varying Structural Parameter Under Thermal Loading

2017 ◽  
Author(s):  
Unique Rahangdale ◽  
Pavan Rajmane ◽  
Abel Misrak ◽  
Dereje Agonafer
Keyword(s):  
Solder Joint ◽  
Copper Content ◽  
Fatigue Cracks ◽  
Dielectric Materials ◽  
Past Study ◽  
Microelectronic Devices ◽  
Wire Bond ◽  
The Common ◽  
Low K ◽  
Different Thickness

The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occur in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with ultra-low-k (ULK) dielectrics flip chip package are used and are facing significant reliability challenges. The ultra-low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. [2] With low modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poorer adhesion of ultra-low-k material, when it is compared to the common dielectric materials, it becomes a major concern to analyze thermomechanical failures. From our past study, it has been concluded that solder joint reliability (SJR) of the small package depends on the copper content in the printed circuit boards (PCB). Also, the wire bond large PBGA packages are a cost-effective package with a substantial number of solder balls. The substrate and PCB have its impact on the solder ball, the mismatch in CTE of different components cause solder failure. In this paper, critical attention has been given to the copper content present in the PCB of different thicknesses and how PCB thickness is related to SJR. The structure of package plays a vital role in deciding reliability of package, as the different structure can shift stress point or distribute stresses to one or more components. The substrate or PCB stack-up or composition can strongly affect the package life. Many parameters need to be studied and package to substrate ratio is one of its which is discussed in this work. Material characterization of PCB with different thickness has been done. Thermal Mechanical Analyzer (TMA) is leveraged to measure temperature-dependent CTE, Dynamic Mechanical Analyzer (DMA) and Universal testing machine are used for measuring Elastic modulus and Poisson’s ratio. Further, a package assembly for the PCB of different thickness has been a model using ANSYS Workbench 18.0.

Integration Challenges for CMP of Copper

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 776-778 ◽  
Author(s):  
Rajeev Bajaj ◽  
Ajoy Zutshi ◽  
Rahul Surana ◽  
Mehul Naik ◽  
Tony Pan
Keyword(s):  
Chemical Mechanical Planarization ◽  
Dielectric Substrate ◽  
Dielectric Films ◽  
Feature Size ◽  
Microelectronic Devices ◽  
Integration Schemes ◽  
New Challenges ◽  
Minimum Feature Size ◽  
Definition Of ◽  
Low K

AbstractAs the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical—mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a Low-κ material, which allows a thicker layer of dielectric to be used. Low-k dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes.1,3–8

Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures

2009 ◽  
Vol 1158 ◽  
Author(s):  
Michael Lane ◽  
Abigail Roush ◽  
Stephen E. Callahan
Keyword(s):  
Dielectric Constant ◽  
Coupling Agents ◽  
Low Dielectric Constant ◽  
Published Data ◽  
Low Dielectric ◽  
Microelectronic Devices ◽  
Potential Impact ◽  
Low K ◽  
Significant Effort ◽  
Improve Reliability

AbstractLow dielectric constant (low-k) materials are currently being incorporated into advanced microelectronic devices to improve or maintain performance. As the dielectric constant is reduced, so are its mechanical properties. These reduced properties have recently been related to chip-package interaction (CPI) failures. Significant effort has focused on eliminating CPI failures through engineering of copper crackstop structures. However, published data suggests that crackstop engineering needs to occur at each technology node to ensure CPI reliability. In this study, the focus is on repairing interfacial delaminations with chemistry specific coupling agents rather than attempting to stop them with a specially designed crackstop structure. Critical adhesion values and corrosion resistance of the repaired interfaces are compared to the original interface. The application of the repair chemistry in an integrated structure is discussed along with the potential impact on reliability.

scholarly journals Measuring the diffusion of Ti and Cu in low-k materials for microelectronic devices by EELS, EFTEM and EDX

2006 ◽  
Vol 26 ◽  
pp. 77-80 ◽  
Author(s):  
J-P Barnes ◽  
D Lafond ◽  
C Guedj ◽  
M Fayolle ◽  
P Meininger ◽  
...  
Keyword(s):  
Microelectronic Devices ◽  
Low K

Characterization of Sputtered Films using the Scanning Electron Microscope

1973 ◽  
Vol 31 ◽  
pp. 44-45
Author(s):  
R. F. Schneidmiller ◽  
W. F. Thrower ◽  
C. Ang
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Sputtered Films ◽  
Plasma Sputtering ◽  
Microelectronic Devices ◽  
Control Film ◽  
Scanning Electron

Solid state materials in the form of thin films have found increasing structural and electronic applications. Among the multitude of thin film deposition techniques, the radio frequency induced plasma sputtering has gained considerable utilization in recent years through advances in equipment design and process improvement, as well as the discovery of the versatility of the process to control film properties. In our laboratory we have used the scanning electron microscope extensively in the direct and indirect characterization of sputtered films for correlation with their physical and electrical properties.Scanning electron microscopy is a powerful tool for the examination of surfaces of solids and for the failure analysis of structural components and microelectronic devices.

Ion Beam Induced Interfacial Reactions in Molybdenum Thin Films on Silicon

1981 ◽  
Vol 39 ◽  
pp. 162-163
Author(s):  
L. J. Chen ◽  
L. S. Hung ◽  
J. W. Mayer
Keyword(s):  
Ion Beam ◽  
Chemical Vapor ◽  
Interfacial Reactions ◽  
Practical Applications ◽  
Microelectronic Devices ◽  
Recent Emergence ◽  
Chemical Vapor Deposited ◽  
Atomic Mixing ◽  
Silicon Interface ◽  
Kinetics Of

When an energetic ion penetrates through an interface between a thin film (of species A) and a substrate (of species B), ion induced atomic mixing may result in an intermixed region (which contains A and B) near the interface. Most ion beam mixing experiments have been directed toward metal-silicon systems, silicide phases are generally obtained, and they are the same as those formed by thermal treatment.Recent emergence of silicide compound as contact material in silicon microelectronic devices is mainly due to the superiority of the silicide-silicon interface in terms of uniformity and thermal stability. It is of great interest to understand the kinetics of the interfacial reactions to provide insights into the nature of ion beam-solid interactions as well as to explore its practical applications in device technology.About 500 Å thick molybdenum was chemical vapor deposited in hydrogen ambient on (001) n-type silicon wafer with substrate temperature maintained at 650-700°C. Samples were supplied by D. M. Brown of General Electric Research & Development Laboratory, Schenectady, NY.

Electron Probe Analysis of Vertebrate Smooth Muscle: Distribution of Ca and Ci

1976 ◽  
Vol 34 ◽  
pp. 334-335 ◽  
Author(s):  
Avril V. Somlyo ◽  
H. Shuman ◽  
A.P. Somlyo
Keyword(s):  
Smooth Muscle ◽  
Electron Probe ◽  
Preliminary Report ◽  
Cell Damage ◽  
Electron Probe Analysis ◽  
Perinuclear Space ◽  
Probe Analysis ◽  
High K ◽  
Low K ◽  
Initial Results

This is a preliminary report of electron probe analysis of rabbit portal-anterior mesenteric vein (PAMV) smooth muscle cryosectioned without fixation or cryoprotection. The instrumentation and method of electron probe quantitation used (1) and our initial results with cardiac (2) and skeletal (3) muscle have been presented elsewhere.In preparations depolarized with high K (K2SO4) solution, significant calcium peaks were detected over the sarcoplasmic reticulum (Fig 1 and 2) and the continuous perinuclear space. In some of the fibers there were also significant (up to 200 mM/kg dry wt) calcium peaks over the mitochondria. However, in smooth muscle that was not depolarized, high mitochondrial Ca was found in fibers that also contained elevated Na and low K (Fig 3). Therefore, the possibility that these Ca-loaded mitochondria are indicative of cell damage remains to be ruled out.

Deposition of Wave-shaped Layered Low-k Dielectric a-C:F Films by C8F18 Plasma CVD

2010 ◽  
Vol 130 (4) ◽  
pp. 319-324
Author(s):  
Kouichiro Mizuno ◽  
Hirotake Sugawara ◽  
Akihiro Murayama
Keyword(s):  
Plasma Cvd ◽  
Low K
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