Reliability Analysis of Ultra-Low-K Large-Die Package and Wire Bond Chip Package on Varying Structural Parameter Under Thermal Loading

2017 ◽  
Author(s):  
Unique Rahangdale ◽  
Pavan Rajmane ◽  
Abel Misrak ◽  
Dereje Agonafer
Keyword(s):  
Solder Joint ◽  
Copper Content ◽  
Fatigue Cracks ◽  
Dielectric Materials ◽  
Past Study ◽  
Microelectronic Devices ◽  
Wire Bond ◽  
The Common ◽  
Low K ◽  
Different Thickness

The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occur in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with ultra-low-k (ULK) dielectrics flip chip package are used and are facing significant reliability challenges. The ultra-low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. [2] With low modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poorer adhesion of ultra-low-k material, when it is compared to the common dielectric materials, it becomes a major concern to analyze thermomechanical failures. From our past study, it has been concluded that solder joint reliability (SJR) of the small package depends on the copper content in the printed circuit boards (PCB). Also, the wire bond large PBGA packages are a cost-effective package with a substantial number of solder balls. The substrate and PCB have its impact on the solder ball, the mismatch in CTE of different components cause solder failure. In this paper, critical attention has been given to the copper content present in the PCB of different thicknesses and how PCB thickness is related to SJR. The structure of package plays a vital role in deciding reliability of package, as the different structure can shift stress point or distribute stresses to one or more components. The substrate or PCB stack-up or composition can strongly affect the package life. Many parameters need to be studied and package to substrate ratio is one of its which is discussed in this work. Material characterization of PCB with different thickness has been done. Thermal Mechanical Analyzer (TMA) is leveraged to measure temperature-dependent CTE, Dynamic Mechanical Analyzer (DMA) and Universal testing machine are used for measuring Elastic modulus and Poisson’s ratio. Further, a package assembly for the PCB of different thickness has been a model using ANSYS Workbench 18.0.

Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity

2006 ◽  
Vol 914 ◽  
Author(s):  
George Andrew Antonelli ◽  
Tran M. Phung ◽  
Clay D. Mortensen ◽  
David Johnson ◽  
Michael D. Goodner ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Coefficient Of Thermal Expansion ◽  
Chemical Vapor ◽  
Dielectric Materials ◽  
Free Standing ◽  
Dielectric Thin Films ◽  
X Ray ◽  
Chemical Vapor Deposited ◽  
Low K

AbstractThe electrical and mechanical properties of low-k dielectric materials have received a great deal of attention in recent years; however, measurements of thermal properties such as the coefficient of thermal expansion remain minimal. This absence of data is due in part to the limited number of experimental techniques capable of measuring this parameter. Even when data does exist, it has generally not been collected on samples of a thickness relevant to current and future integrated processes. We present a procedure for using x-ray reflectivity to measure the coefficient of thermal expansion of sub-micron dielectric thin films. In particular, we elucidate the thin film mechanics required to extract this parameter for a supported film as opposed to a free-standing film. Results of measurements for a series of plasma-enhanced chemical vapor deposited and spin-on low-k dielectric thin films will be provided and compared.

Top down nano technologies in surface modification of materials

Open Physics ◽  
2011 ◽  
Vol 9 (2) ◽  
Author(s):  
Branislav Radjenović ◽  
Marija Radmilović-Radjenović
Keyword(s):  
Surface Modification ◽  
Three Dimensional ◽  
Wet Etching ◽  
Plasma Reactors ◽  
Top Down ◽  
Isotropic Etching ◽  
Microelectronic Devices ◽  
Etching Profile ◽  
Simulation Results ◽  
Low K

AbstractThis article contains a broad overview of etch process as one of the most important top-down technologies widely used in semiconductor manufacturing and surface modification of nanostructures. In plasma etching process, the complexity comes from the introduction of new materials and from the constant reduction in dimensions of the structures in microelectronics. The emphasis was made on two types of etching processes: dry etching and wet etching illustrated by three dimensional (3D) simulation results for the etching profile evolution based on the level set method. The etching of low-k dielectrics has been demonstrated via modelling the porous materials. Finally, simulation results for the roughness formation during isotropic etching of nanocomposite materials as well as smoothing of the homogeneous materials have also been shown and analyzed. Simulation results, presented here, indicate that with shrinking microelectronic devices, plasma and wet etching interpretative and predictive modeling and simulation have become increasingly more attractive as a tool for design, control and optimization of plasma reactors.

Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

Thermal conductivity study of porous low-k dielectric materials

2000 ◽  
Vol 77 (1) ◽  
pp. 145-147 ◽  
Author(s):  
Chuan Hu ◽  
Michael Morgen ◽  
Paul S. Ho ◽  
Anurag Jain ◽  
William N. Gill ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Dielectric Materials ◽  
Low K

Improving Stitch Bond on Hybrid Thick Film Substrate using Stand-Off Stitch Wire Bond Technique

2015 ◽  
Vol 2015 (1) ◽  
pp. 000425-000429 ◽  
Author(s):  
Richard C. Garcia
Keyword(s):  
Thick Film ◽  
Dielectric Materials ◽  
Glass Frit ◽  
Ceramic Substrate ◽  
Wire Bond ◽  
Design Requirements ◽  
The Wire ◽  
Film Substrate ◽  
Pull Tests ◽  
Associated Variables

Thick film technology is based on a paste containing glass frit that is screen printed and fused at high temperature onto various ceramic substrate materials. Softening or melting this glassy frit forms a cohesive layer, binding the conductors, resistors or dielectric materials to the ceramic. The dynamics of the printing process and inherent number of associated variables negatively impact the uniformity of the fired surface on a micro scale, which can lead to variation in the wire bonding process. Other processes associated with thick film substrate fabrication can cause problems as well. Laser trimming is used to adjust the value of printed resistors to meet design requirements. This ablation of printed resistors by high–powered pulse laser leaves a halo of debris and contamination on the ceramic substrate, which can cause wire bond lifting. In this paper, we will demonstrate a way to eliminate these problems using a bonding technique called Stand- Off Stitch bonding (SOS). This wire bond type is formed by first placing a ball bump at the second bond, or stitch, location on the thick film substrate, and then forming a normal wire that terminates on that bump. This places two ball bumps at each end of the wire, similar to a security bond. However, the ball bump is located under the stitch instead of on top. This SOS wire bond technique is compliant with the MIL-STD- 883 for a compound bond, where one bond is placed on top of another bond. With the gold bump placed on top of the gold thick film pad, the bump acts as a foundation for the stitch bond, providing a wider contact area and clean bond surface to secure a reliable stitch bond interconnect. With this change, an abrupt improvement to the resultant destruct wire pull tests can be achieved, promoting a robust, controlled process for wire bond interconnects.

Thermal conductivity study of porous low K dielectric materials

1999 ◽  
Vol 565 ◽  
Author(s):  
Chuan Hu ◽  
Michael Morgen ◽  
Paul S. Ho ◽  
Anurag Jain ◽  
William. N. Gill ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Dielectric Materials ◽  
Porous Films ◽  
Low Dielectric ◽  
Omega Method ◽  
3 Omega ◽  
Low Dielectric Constant Materials ◽  
Low K ◽  
Method Analysis

AbstractA quantitative characterization of the thermal properties is required to assess the thermal performance of low dielectric constant materials. Recently we have developed a technique based on the 3-omega method for measuring the thermal conductivity of porous dielectric thin films. In this paper we present the results on the measurements of thermal conductivity of thin porous films using this method. A finite element method analysis is used to evaluate the approximations used in the measurement. Two porosity-weighted thermal resistor models are proposed to interpret the results. By studying the dependence of the thermal conductivity on porosity, we are able to discuss the scaling rule of thermal conductivity. Additionally, a steady state layered heater model is used for evaluating the significance of introducing porous ILDs into an interconnect structure.

Subcritical Delamination of Dielectric and Metal Films from Low-k Organosilicate Glass (OSG) Thin Films in Buffered pH Solutions

2003 ◽  
Vol 795 ◽  
Author(s):  
Y. Lin ◽  
J. J. Vlassak ◽  
T. Y. Tsui ◽  
A. J. McKerrow
Keyword(s):  
Thin Films ◽  
Ph Value ◽  
Dielectric Materials ◽  
Barrier Films ◽  
Interface Delamination ◽  
Organosilicate Glass ◽  
Controlled Fracture ◽  
Ph Buffer ◽  
Subcritical Fracture ◽  
Low K

ABSTRACTUnderstanding subcritical fracture of low-k dielectric materials and barrier thin films in buffered solutions of different pH value is of both technical and scientific importance. Subcritical delamination of dielectric and metal barrier films from low-k organosilicate glass (OSG) films in pH buffer solutions was studied in this work. Crack path and subcritical fracture behavior of OSG depends on the choice of barrier layers. For the OSG/TaN system, fracture takes place in the OSG layer near the interface, while in OSG/SiNx system, delamination occurs at the interface. Delamination behavior of both systems is well described by a hyperbolic sine model that had been developed previously based on a chemical reaction controlled fracture process at the crack tip. The threshold toughness of both systems decreases linearly with increasing pH value. The slopes of the reaction-controlled regime of the crack velocity curves for both systems are independent of pH as predicted by the model. Near transport-controlled regime behavior was observed in OSG/TaN system.

Designing Ultra Low-k Dielectric Materials for Ease of Patterning

2010 ◽  
Vol 1249 ◽  
Author(s):  
George Andrew Antonelli ◽  
Gengwei Jiang ◽  
Mandyam Sriram ◽  
Kaushik Chattopadhyay ◽  
Wei Guo ◽  
...  
Keyword(s):  
Inductively Coupled Plasma ◽  
Ion Beam ◽  
Plasma Reactor ◽  
Dielectric Materials ◽  
Dielectric Constants ◽  
Interlayer Dielectric ◽  
Inductively Coupled ◽  
Inductively Coupled Plasma Reactor ◽  
Low K

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

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