scholarly journals Ultra-Low-Temperature Cofired Ceramic Substrates with Low Residual Carbon for Next-Generation Microwave Applications

2019 ◽  
Vol 11 (26) ◽  
pp. 23798-23807 ◽  
Author(s):  
Nina Joseph ◽  
Jobin Varghese ◽  
Merja Teirikangas ◽  
Timo Vahera ◽  
Heli Jantunen
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Piotr Kowalik ◽  
Edyta Wróbel

Purpose This paper aims to present the possibility of computer-aided technology of chemical metallization for the production of electrodes and resistors based on Ni-P and Ni-Cu-P layers. Design/methodology/approach Based on the calculated parameters of the process, test structures were made on an alumina substrate using the selective metallization method. Dependences of the surface resistance on the metallization time were made. These dependencies take into account the comparison of the calculations with the performed experiment. Findings The author created a convenient and easy-to-use tool for calculating basic Ni-P and Ni-Cu-P layer parameters, namely, surface resistance and temperature coefficient of resistance (TCR) of test resistor, based on chemical metallization parameters. The values are calculated for a given level of surface resistance of Ni-P and Ni-Cu-P layer and defined required range of changes of TCR of test resistor. The calculations are possible for surface resistance values in the range of 0.4 Ohm/square ÷ 2.5 Ohm/square. As a result of the experiment, surface resistances were obtained that practically coincide with the calculations made with the use of the program created by the authors. The quality of the structures made is very good. Originality/value To the best of the authors’ knowledge, the paper presents a new, unpublished method of manufacturing electrodes (resistors) on silicon, Al2O3 and low temperature co-fired ceramic substrates based on the authors developed computer program.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.


Author(s):  
Eugene M. Chow

Lithographically defined spring electrical contacts have many applications for next generation electronics test and packaging. The springs can lower the cost of multi-chip modules because their rework ability addresses the known-good-die problem. Lower height chip stacking for mobile electronics markets is enabled because a sliding spring can have a much shorter profile than solder. Larger die can be directly bonded to the board because the compliance absorbs thermal expansion mismatches between substrates. Significant stress isolation is possible, which is important for mechanically sensitive die such as MEMS and low K die. Very high density is possible, as 6 (am pitch has been demonstrated. Fabrication is scalable and assembly is low temperature. This paper reviews our prototype demonstrations for these applications as well as relevant reliability data and contact studies.


2005 ◽  
Vol 28 (1) ◽  
pp. 121-127 ◽  
Author(s):  
V. Heikkinen ◽  
J. Aikio ◽  
T. Alajoki ◽  
K. Kautio ◽  
J. Ollila ◽  
...  

ACS Nano ◽  
2017 ◽  
Vol 11 (8) ◽  
pp. 7710-7718 ◽  
Author(s):  
Rui Yang ◽  
Yang Wang ◽  
Dang Wu ◽  
Yubin Deng ◽  
Yingying Luo ◽  
...  

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