Low Temperature Curing - Aqueous Base Developable Photoimageable Dielectric for WLP (Wafer Level Packaging)

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Low Temperature ◽  
Dielectric Material ◽  
Broad Band ◽  
Dielectric Materials ◽  
Next Generation ◽  
Wafer Level ◽  
Moore’S Law ◽  
Moore's Law ◽  
3D Chip Stacking ◽  
The Impact

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.

Low Temperature Curable PI/PBO for Advanced Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15 ◽  
Author(s):  
Daisaku Matsukawa ◽  
Tadamitsu Nakamura ◽  
Tetsuya Enomoto ◽  
Noriyuki Yamazaki ◽  
Masayuki Ohe ◽  
...  
Keyword(s):  
Low Temperature ◽  
Chemical Resistance ◽  
High Reliability ◽  
Dielectric Materials ◽  
The Novel ◽  
Next Generation ◽  
Wafer Level ◽  
High Chemical ◽  
High Chemical Resistance ◽  
Advanced Packaging

Photo-definable polyimides (PI) and polybenzoxazoles (PBO) have been widely used as dielectrics for re-distribution layers in wafer level chip size packages (WL-CSP). These materials can simplify the manufacturing process and ensure high reliability owing to their good mechanical properties and high thermal stability. For next generation electronic components fabricated by utilizing advanced packaging technologies such as 3D-stacking using TSV, package-on-package, fan-out WL-CSP etc., the most important requirements for dielectric materials are high lithographic performance, high adhesion to Cu RDL, high chemical resistance and low temperature curability. In this paper, we will report on our novel low temperature (<200C) curable PBO and PI. A novel alkaline positive tone PBO was developed by re-designing key components of the formulation to enhance lithographic performance, Cu adhesion and chemical resistance. It was found that the new PBO material showed higher lithographic performance than conventional PBOs due to its high dissolution contrast and which resulted in a resolution of 2micron (L/S) with a 7μm cured thickness and 3micron (L/S) with a 15micron cured thickness, respectively. This material also produced strong Cu adhesion and high chemical resistance at curing temperatures <200C with no delamination from the Cu RDL being observed after a 168hr Pressure Cooker Test (PCT). Furthermore, the new formulation showed high TCT resistance due to its high elongation below 0C. In addition, a novel solvent negative tone PI was also developed by incorporating a cross-linker to accelerate low temperature curability as well a photo-initiator to improve lithographic properties. As a result, the novel PI when cured at 175C for 1hr showed high Cu adhesion after 168hr PCT as well as high film properties. The new PI also showed excellent lithographic properties with a resolution of 6micron (L/S). Furthermore, the low temperature curable PI and PBO materials were used as dielectrics to fabricate WL-CSPs for both chip and board level reliability testing. The test results indicated that both the novel PBO and PI showed excellent reliability after thermal cycling (TCT) due to the significant improvements made to Cu adhesion and chemical resistance. These materials are expected to be promising for next generation WLP applications. Details are described in the presentation.

Drain Current Model for Hetero-Dielectric Based TFET Architectures: Accumulation to Inversion Mode Analysis

2015 ◽  
Vol 36 ◽  
pp. 31-43
Author(s):  
Upasana ◽  
Rakhi Narang ◽  
Manoj Saxena ◽  
Mridula Gupta
Keyword(s):  
Dielectric Material ◽  
Current Model ◽  
Dynamic Performance ◽  
Drain Current ◽  
Dielectric Materials ◽  
Mode Analysis ◽  
Length Variation ◽  
Inversion Mode ◽  
Depth Study ◽  
The Impact

The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the Vgs and Vds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both Ids-Vds and Ids-Vds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, Ion/Ioff ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (Cgg), gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.

scholarly journals Towards a Thermal Moore’s Law

2005 ◽  
Author(s):  
Shankar Krishnan ◽  
Suresh V. Garimella ◽  
Greg M. Chrysler ◽  
Ravi V. Mahajan
Keyword(s):  
Heat Sink ◽  
High Efficiency ◽  
Thermal Design ◽  
Air Cooling ◽  
Thermoelectric Coolers ◽  
Moore’S Law ◽  
Moore's Law ◽  
The Impact ◽  
Power Densities ◽  
Design Power

The thermal design power trends and power densities for present and future microprocessors are investigated. The trends are derived based on Moore’s law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of the projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of an air-cooling limit consistent with Moore’s law is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.

Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study

2021 ◽  
pp. 105141
Author(s):  
J. Ajayan ◽  
D. Nirmal ◽  
Shubham Tayal ◽  
Sandip Bhattacharya ◽  
L. Arivazhagan ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Next Generation ◽  
Intensive Study ◽  
Moore’S Law ◽  
Moore's Law

Dielectric Laser Via Drilling for Next Generation Wafer Level Processing

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000863-000885
Author(s):  
Jim Zaccardi ◽  
Guy Burgess ◽  
Theodore Tessier ◽  
Ken Lafenhagen ◽  
Matt Souter
Keyword(s):  
State Of The Art ◽  
Dielectric Materials ◽  
Formation Processes ◽  
Next Generation ◽  
Wafer Level ◽  
Ablation Process ◽  
Design Rules ◽  
Laser Ablation Process ◽  
The Common ◽  
Feature Resolution

The common via formation processes used today for dielectrics in WLCSP RDL and flipchip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes. There is considerable interest in using laser via drilling (ablation) in dielectrics for flipchip, RDL inner layer, and WLCSP processing for reduced via dimensions and enabling a broader range of dielectric materials, including inherently non-photosensitive options. This presentation will demonstrate “state of the art” laser ablation process results, through different dielectrics showing improved feature resolution and reduced via opening sizes resulting in significantly improved interconnect density. Laser via drilling is a more simplified process compared to traditional photolithography methods. This presentation will demonstrate how using laser via drilling could dramatically improve the design rules for next generation RDL designs.

New Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and High Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000466-000469 ◽  
Author(s):  
Daichi Okamoto ◽  
Yoko Shibasaki ◽  
Daisuke Shibata ◽  
Tadahiko Hanada
Keyword(s):  
Residual Stress ◽  
Low Temperature ◽  
Dielectric Material ◽  
High Reliability ◽  
Dielectric Materials ◽  
High Density ◽  
Curing Temperature ◽  
Temperature Cycle ◽  
Curing Process ◽  
Additive Process

Abstract This paper presents an advanced ultra-thin photosensitive dielectric Film (PDM) newly developed with high resolution, low CTE and low residual stress for next-generation high-density redistribution layer (RDL), 2.5D interposer, and high-density fan-out package applications. For high-density RDL, photosensitive dielectric materials need to have low CTE to achieve high package reliability. The CTE of the material is 30–35ppm/K. While maintaining the low CTE, we successfully demonstrated the minimum micro-via diameter of 3um in the 5um thickness. Curing temperature of the PDM is 180°C × 60 min. which is lower than most of the advanced dielectric materials which currently used in industry. Low-temperature curing process results in low stress. We have calculated residual stress in the cured PDM from a test result of warpage measurement on 4 inch wafer. As another benefit of the PDM material in curing process, the PDM can be cured in air oven. Most of advanced photo dielectric materials need to cure in N2 oven due to prevent an oxidation of the material. We have demonstrated copper traces of 2um lines and spaced on the PDM by using semi-additive process (SAP) with sputtered Ti/Cu seed layer. Thanks to the low CTE and low residual stress due to the low-temperature curing, it passed temperature cycle test (1,000 cycles) with daisy chain structure which has 400 vias in the structure. It can be concluded that the newly developed PDM is a promising dielectric material for highly reliable high-density redistribution layer (RDL) for 2.5D interposers and fan-out wafer level package applications.

The Impact of Moore's Law

2006 ◽  
Vol 11 (3) ◽  
pp. 25-27 ◽  
Author(s):  
Robert W. Keyes
Keyword(s):  
Moore’S Law ◽  
Moore's Law ◽  
The Impact
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