Electrical characteristics of a metal–insulator–semiconductor memory structure containing Ge nanocrystals

2005 ◽  
Vol 26 (1-4) ◽  
pp. 386-390 ◽  
Author(s):  
C.L. Heng ◽  
T.G. Finstad
Keyword(s):  
Memory Structure ◽  
Electrical Characteristics ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Ge Nanocrystals

Abnormal Capacitance Hysteresis Phenomena in Stacked Nanocrystalline-Si Based Metal Insulator Semiconductor Memory Structure

2012 ◽  
Vol 531-532 ◽  
pp. 547-550
Author(s):  
Xiang Wang ◽  
Song Chao ◽  
Yan Qing Guo ◽  
Jie Song ◽  
Rui Huang
Keyword(s):  
Chemical Vapor ◽  
Memory Structure ◽  
Layer By Layer ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Effect Model ◽  
Flatband Voltage ◽  
Hysteresis Phenomena ◽  
Nanocrystalline Si

Stack nanocrystalline-Si (nc-Si) based metal insulator semiconductor memory structure was fabricated by plasma enhanced chemical vapor deposition. The doubly stacked layers of nc-Si with the thickness of about 5 nm were fabricated by the layer-by-layer deposition technique with silane and hydrogen mixture gas. Capacitance-Voltage (C-V) measurements were used to investigate electron tunnel and storage characteristic. Abnormal capacitance hysteresis phenomena are obtained. The C-V results show that the flatband voltage increases at first, then decreases and finally increases, exhibiting a clear deep at gate voltage of 9 V. The charge transfer effect model was put forward to explain the electron storage and discharging mechanism of the stacked nc-Si based memory structure. The decreasing of flatband voltage at moderate programming bias is attributed to the transfer of electrons from the lower nc-Si layer to the upper nc-Si layer.

Charge retention enhancement in stack nanocrystalline-Si based metal-insulator-semiconductor memory structure

2006 ◽  
Vol 89 (11) ◽  
pp. 112118 ◽  
Author(s):  
L. C. Wu ◽  
K. J. Chen ◽  
J. M. Wang ◽  
X. F. Huang ◽  
Z. T. Song ◽  
...  
Keyword(s):  
Memory Structure ◽  
Charge Retention ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Nanocrystalline Si

Electrical characteristics of DNA-based metal-insulator-semiconductor structures

2010 ◽  
Vol 107 (12) ◽  
pp. 124518 ◽  
Author(s):  
S. Sönmezoğlu ◽  
Ö. Ateş Sönmezoğlu ◽  
G. Çankaya ◽  
A. Yıldırım ◽  
N. Serin
Keyword(s):  
Electrical Characteristics ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Semiconductor Structures

Manipulation of Germanium Nanocrystals in a Tri-Layer Insulator Structure of a Metal-Insulator-Semiconductor Memory Device

2002 ◽  
Vol 728 ◽  
Author(s):  
L.W. Teo ◽  
C.L. Heng ◽  
V. Ho ◽  
M. Tay ◽  
W.K. Choi ◽  
...  
Keyword(s):  
Silicon Dioxide ◽  
Oxide Layer ◽  
Layer Structure ◽  
Charge Trapping ◽  
Middle Layer ◽  
Memory Device ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
20 Nm ◽  
Ge Nanocrystals

AbstractA metal-insulator-semiconductor (MIS) device that consists of germanium (Ge) nanocrystals embedded in a novel tri-layer insulator structure is proposed for memory applications [1]. The tri-layer structure comprises a thin (≈5nm) rapid thermal oxidation (RTO) silicon dioxide (SiO2) layer, a Ge+SiO2 middle layer (6 - 20 nm) deposited by RF co-sputtering technique and a RF-sputtered silicon dioxide capping layer. High-resolution transmission electron microscopy (HRTEM) results show that Ge nanocrystals of sizes ranging from 6 –20 nm were found after rapid thermal annealing of the trilayer structure at 1000°C for 300s. The electrical properties of these devices have been characterized using capacitance versus voltage (C-V) measurements. A significant hysteresis was observed in the C-V curves of these devices, indicating charge trapping in the composite insulator. Comparison with devices having similar tri-layer insulator structure, but with a pure sputtered oxide middle layer (i.e. minus the Ge nanocrystals), clearly indicated that the observed charge trapping is due to the presence of the Ge nanocrystals in the middle layer. The C-V measurements of devices without the capping SiO2 layer exhibited no significant hysteresis as compared to the embedded Ge nanocrystal tri-layer devices. The HRTEM micrographs showed that the presence of the capping oxide is critical in the formation of nanocrystals for this structure. By varying the thickness of the middle layer, it was found that the maximum nanocrystal size correlates well with the middle layer thickness. This indicates that the nanocrystals are well confined by the RTO oxide layer and the capping oxide layer. In addition, Ge nanocrystals formed using a thinner middle layer were found to be relatively uniform in size and distribution. This structure, therefore, offers a possibility of fabricating memory devices with controllable Ge nanocrystals size.

Effects of Interface Nitride Layer on Electrical Characteristics of SiO2/Nitride/SiC Metal–Insulator–Semiconductor Diode

2011 ◽  
Vol 50 (1S2) ◽  
pp. 01BG02 ◽  
Author(s):  
Tomohiko Yamakami ◽  
Shinichiro Suzuki ◽  
Mitsunori Henmi ◽  
Yusuke Murata ◽  
Rinpei Hayashibe ◽  
...  
Keyword(s):  
Nitride Layer ◽  
Semiconductor Diode ◽  
Electrical Characteristics ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor
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