Charge retention enhancement in stack nanocrystalline-Si based metal-insulator-semiconductor memory structure

2006 ◽  
Vol 89 (11) ◽  
pp. 112118 ◽  
Author(s):  
L. C. Wu ◽  
K. J. Chen ◽  
J. M. Wang ◽  
X. F. Huang ◽  
Z. T. Song ◽  
...  
Keyword(s):  
Memory Structure ◽  
Charge Retention ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Nanocrystalline Si

Abnormal Capacitance Hysteresis Phenomena in Stacked Nanocrystalline-Si Based Metal Insulator Semiconductor Memory Structure

2012 ◽  
Vol 531-532 ◽  
pp. 547-550
Author(s):  
Xiang Wang ◽  
Song Chao ◽  
Yan Qing Guo ◽  
Jie Song ◽  
Rui Huang
Keyword(s):  
Chemical Vapor ◽  
Memory Structure ◽  
Layer By Layer ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Effect Model ◽  
Flatband Voltage ◽  
Hysteresis Phenomena ◽  
Nanocrystalline Si

Stack nanocrystalline-Si (nc-Si) based metal insulator semiconductor memory structure was fabricated by plasma enhanced chemical vapor deposition. The doubly stacked layers of nc-Si with the thickness of about 5 nm were fabricated by the layer-by-layer deposition technique with silane and hydrogen mixture gas. Capacitance-Voltage (C-V) measurements were used to investigate electron tunnel and storage characteristic. Abnormal capacitance hysteresis phenomena are obtained. The C-V results show that the flatband voltage increases at first, then decreases and finally increases, exhibiting a clear deep at gate voltage of 9 V. The charge transfer effect model was put forward to explain the electron storage and discharging mechanism of the stacked nc-Si based memory structure. The decreasing of flatband voltage at moderate programming bias is attributed to the transfer of electrons from the lower nc-Si layer to the upper nc-Si layer.

Charge retention characteristics in a metal insulator semiconductor capacitor containing Ge nanocrystals

2002 ◽  
Vol 17 (10) ◽  
pp. 1039-1043 ◽  
Author(s):  
Yong Kim ◽  
Hea Jeong Cheong ◽  
Kyung Hwa Park ◽  
Tae Hun Chung ◽  
Hong Jun Bark ◽  
...  
Keyword(s):  
Charge Retention ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Retention Characteristics ◽  
Ge Nanocrystals

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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