Control of interfacial charges of organic semiconductor by a surface polarized layer for high noise-margin inverters with full-swing capability

2012 ◽  
Vol 13 (11) ◽  
pp. 2365-2371 ◽  
Author(s):  
Min-Hoi Kim ◽  
Seung-Peom Noh ◽  
Chang-Min Keum ◽  
Jin-Hyuk Bae ◽  
Sin-Doo Lee
Keyword(s):  
Organic Semiconductor ◽  
High Noise ◽  
Noise Margin ◽  
Full Swing

Low-voltage flexible organic complementary inverters with high noise margin and high dc gain

2009 ◽  
Vol 94 (4) ◽  
pp. 043312 ◽  
Author(s):  
Xiao-Hong Zhang ◽  
William J. Potscavage ◽  
Seungkeun Choi ◽  
Bernard Kippelen
Keyword(s):  
Low Voltage ◽  
High Noise ◽  
Noise Margin ◽  
Dc Gain ◽  
Complementary Inverters

scholarly journals Reduced Voltage Scaling in Clock Distribution Networks

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-7 ◽  
Author(s):  
Khader Mohammad ◽  
Ayman Dodin ◽  
Bao Liu ◽  
Sos Agaian
Keyword(s):  
Low Voltage ◽  
Distribution Networks ◽  
Power Reduction ◽  
Active Power ◽  
Minimum Area ◽  
Clock Distribution Networks ◽  
Noise Margin ◽  
Voltage Swing ◽  
Full Swing ◽  
Circuit Technique

We propose a novel circuit technique to generate a reduced voltage swing (RVS) signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV) devices and the programmability of the low voltage value.

Flexible and high noise margin organic enhancement inverter using hybrid insulator

2017 ◽  
Vol 622 ◽  
pp. 29-33 ◽  
Author(s):  
Dong-Hoon Lee ◽  
Jinsu Kim ◽  
Hyeong-Jun Cho ◽  
Min Su Kim ◽  
Eung-Kyu Park ◽  
...  
Keyword(s):  
High Noise ◽  
Noise Margin

scholarly journals High noise margin decoding of holographic data page based on compressed sensing

2020 ◽  
Vol 28 (5) ◽  
pp. 7139
Author(s):  
Jinpeng Liu ◽  
Le Zhang ◽  
Anan Wu ◽  
Yoshito Tanaka ◽  
Masanobu Shigaki ◽  
...  
Keyword(s):  
Compressed Sensing ◽  
High Noise ◽  
Noise Margin ◽  
Data Page

scholarly journals Low storage power and high noise margin ternary memory cells in nanoelectronics

2020 ◽  
Vol 14 (7) ◽  
pp. 929-941 ◽  
Author(s):  
Seied Ali Hosseini ◽  
Sajjad Etezadi
Keyword(s):  
Memory Cells ◽  
High Noise ◽  
Noise Margin
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