Low-voltage flexible organic complementary inverters with high noise margin and high dc gain

2009 ◽  
Vol 94 (4) ◽  
pp. 043312 ◽  
Author(s):  
Xiao-Hong Zhang ◽  
William J. Potscavage ◽  
Seungkeun Choi ◽  
Bernard Kippelen
Keyword(s):  
Low Voltage ◽  
High Noise ◽  
Noise Margin ◽  
Dc Gain ◽  
Complementary Inverters

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

Low voltage, high gain electrolyte-gated complementary inverters based on transfer-printed block copolymer ion gels

2019 ◽  
Vol 71 ◽  
pp. 266-271 ◽  
Author(s):  
Donghui Lee ◽  
Kyung Gook Cho ◽  
Kyoung Hwan Seol ◽  
Sangho Lee ◽  
Soo-Hyung Choi ◽  
...  
Keyword(s):  
Block Copolymer ◽  
Low Voltage ◽  
High Gain ◽  
Complementary Inverters ◽  
Ion Gels

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

Photo-patternable high-k ZrOx dielectrics prepared using zirconium acrylate for low-voltage-operating organic complementary inverters

2016 ◽  
Vol 33 ◽  
pp. 40-47 ◽  
Author(s):  
Yong Jin Jeong ◽  
Dong-Jin Yun ◽  
Sooji Nam ◽  
Eui Hyun Suh ◽  
Chan Eon Park ◽  
...  
Keyword(s):  
Low Voltage ◽  
High K ◽  
Complementary Inverters
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