Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

2009 ◽  
Vol 49 (9-11) ◽  
pp. 1048-1051 ◽  
Author(s):  
N. Berbel ◽  
R. Fernandez ◽  
I. Gil
Keyword(s):  
Experimental Verification ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Cmos Inverter ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
The Impact

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

2007 ◽  
Vol 17 (01) ◽  
pp. 129-141
Author(s):  
N. A. CHOWDHURY ◽  
D. MISRA ◽  
N. RAHIM
Keyword(s):  
Interface State ◽  
Initial Time ◽  
Negative Bias ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High Bias ◽  
The Impact

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

scholarly journals Impact of NBTI Stress on VDMOSFET Regions

2018 ◽  
Vol 3 (2) ◽  
pp. 65-69
Author(s):  
Sidi Mohammed Merah ◽  
Bouchra Nadji
Keyword(s):  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Mos Transistor ◽  
Bias Temperature Instability ◽  
Capacitance Voltage ◽  
Drain Region ◽  
Phosphorus Doped ◽  
The Impact

In this paper, we investigate the impact of negative bias temperature instability (NBTI) degradation on both channel and drain regions, of commercial power double diffused MOS transistor (VDMOSFET), using capacitance-voltage method (C-V). We report that the degradation is important at channel (drain) region in p-channel VDMOSFET (n-channel VDMOSFET). That means that the phosphorus doped region (n-type) is more sensitive to NBTI stress.

Negative Bias Temperature Instability for P-channel of LTPS Thin Film Transistors with Fluorine Implantation

2008 ◽  
Vol 1066 ◽  
Author(s):  
Chyuan-Haur Kao ◽  
W. H. Sung
Keyword(s):  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Negative Bias ◽  
Electrical Characteristics ◽  
Trap States ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
The Impact

ABSTRACTThis paper studies the impact of LTPS (low temperature polycrystalline silicon) TFTs with fluorine implantation under NBTI (Negative bias temperature instability) stress. The fluorinated TFTs' devices can obtain better characteristics with samller threshold voltage shift, lower trap states and lower subthreshold swing variation. Therefore, the fluorine implantation does not only improve initial electrical characteristics, but also suppresses the NBTI-induced degradation.

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